Advait Mogre

MetaCores: design and optimization techniques

Hardware intellectual property (IP) is delivered at three levels of abstraction: hard, firm, and soft. In order to further enhance performance, efficiency, and flexibility of IP design, we have developed a new approach for designing hardware and software IP called MetaCores. The new design approach starts at the algorithm level and leverages on the algorithms intrinsic optimization degrees of freedom. The approach has four main components: (i) problem formulation and identification of optimization degrees of freedom, (ii) objective functions and constraints, (iii) cost evaluation engine, and (iv) multiresolution design space search. From the algorithmic viewpoint, the main contribution is the introduction of multiresolution search in algorithm optimization and synthesis process. We have applied the approach to the development of Viterbi and IIR MetaCores. Experimental results demonstrate the effectiveness of the new approach.

A single-chip concatenated FEC decoder

A single chip decoder, which implements the concatenated forward error correction functions for a digital satellite receiver system, has been designed. The functions include Viterbi decoding, convolutional deinterleaving, Reed-Solomon decoding, data stream synchronization and descrambling. The device has been fabricated in a 0.6 /spl mu/m CMOS cell-based technology and is fully functional at data rates of 73 Mbits/sec at 70/spl deg/C and 4.75 V.

A two-stage decoder for pragmatic trellis-coded M-PSK modulation using a symbol transformation

A two-stage decoding procedure for pragmatic trellis-coded modulation (TCM) is introduced. It applies a transformation from the received I-channel and Q-channel samples onto points in a two-dimensional (2-D) signal space that contains a coset constellation. For pragmatic TCM over M-PSK signal sets with /spl nu/ coded bits per symbol, /spl nu/=1, 2, the signal points in the coset constellations represent cosets of a B/QPSK signal subset-associated with the coded bits-in the original M-PSK signal constellation. A conventional Viterbi decoder operates on the transformed symbols to estimate the coded bits. After reencoding these bits, the uncoded bits are estimated in a second stage, on a symbol-by-symbol basis, with decisions based on the location of the received symbols. In addition to requiring no changes in the Viterbi decoder core, it is shown that the proposed method results in savings of up to 40% in the memory required to store (or in the size of the logic required to compute) metrics and transformed symbols.

Invariancies in punctured convolutional codes-their effect on Viterbi synchronization

This paper studies the invariance of a given punctured convolutional code to an affine class of symbol transformations known to commonly occur in digital transceiver systems. A set of conditions to test the invariance of a code to these transformations has been derived, followed by two proposed methods to compensate for an invariant transformation. The viability of these methods has been examined by doing an invariant factor decomposition on the equivalent code generator matrix (obtained from the original code generator matrix and the given transform). The knowledge of the transformation and the nature of its occurrence greatly determines which method of compensation could be used. This study has much use in not only enabling a code designer to evaluate the invariance of an affine transformation to a given code, but also on the other hand to make the appropriate choice of code generators, puncturing schemes, and bit-to-constellation symbol mapping; so as to allow a channel coding scheme to be either sensitive or invariant to a given transformation, depending upon design objectives.