Daniel A. Luthi

A video-rate JPEG chip set

A two-chip set has been designed, fabricated and is fully functional which performs the baseline JPEG image compression and decompression algorithm. The major functions of the devices include: DCT and IDCT, forward and inverse quantization, Huffman coding and decoding. The devices operate with pixel rates beyond 30 MHz at 70 degrees C and 4.75 V. Each die is less than 10 mm on a side and was implemented in a 1.0 µ CMOS cell-based technology to achieve a 9 man-month design time.

A single-chip concatenated FEC decoder

A single chip decoder, which implements the concatenated forward error correction functions for a digital satellite receiver system, has been designed. The functions include Viterbi decoding, convolutional deinterleaving, Reed-Solomon decoding, data stream synchronization and descrambling. The device has been fabricated in a 0.6 /spl mu/m CMOS cell-based technology and is fully functional at data rates of 73 Mbits/sec at 70/spl deg/C and 4.75 V.

A reconfigurable 64-tap transversal filter

A high-speed transversal filter processor with 64 8-bit multiplier accumulators using several innovative custom design techniques has been realized in 14-mm*14-mm silicon at 20-MHz speeds. The processor (L64240) can be configured as a one-dimensional filter for radar or as a two-dimensional filter for real-time image applications. The authors describe the internal architecture of the filter, its key components, and the critical concerns addressing the speed and size of the design.<<ETX>>

A Video-rate Jpeg Chip Set

A two-chip set has been designed, fabricated and is fully functional which performs the baseline JPEG image compression and decompression algorithm. The major functions of the devices include: DCT and IDCT, forward and inverse quantization, Huffman coding and decoding. The devices operate with pixel rates beyond 30 MHz at 70 degrees C and 4.75 V. Each die is less than 10 mm on a side and was implemented in a 1.0 µ CMOS cell-based technology to achieve a 9 man-month design time.

A 40 MHz programmable and reconfigurable filter processor

A programmable and reconfigurable filter processor comprising four 16*16 multiplier-accumulators is presented. The processor, fabricated in a 1.5- mu m 2-layer metal CMOS process, has been tested and is fully functional up to 40 MHz clock frequency. It can be programmed and reconfigured via an on-chip sequencer for a range of applications, including radar signal processing, image processing, discrete cosine transform, discrete Fourier transform, and other general inner product applications.<<ETX>>

Invariancies in punctured convolutional codes-their effect on Viterbi synchronization

This paper studies the invariance of a given punctured convolutional code to an affine class of symbol transformations known to commonly occur in digital transceiver systems. A set of conditions to test the invariance of a code to these transformations has been derived, followed by two proposed methods to compensate for an invariant transformation. The viability of these methods has been examined by doing an invariant factor decomposition on the equivalent code generator matrix (obtained from the original code generator matrix and the given transform). The knowledge of the transformation and the nature of its occurrence greatly determines which method of compensation could be used. This study has much use in not only enabling a code designer to evaluate the invariance of an affine transformation to a given code, but also on the other hand to make the appropriate choice of code generators, puncturing schemes, and bit-to-constellation symbol mapping; so as to allow a channel coding scheme to be either sensitive or invariant to a given transformation, depending upon design objectives.

Design of a 20 MHz 64-tap transversal filter

The authors describe the architecture and design of a high-speed CMOS VLSI filter processor. The internal architecture of the design is pipelined to achieve a sustained 20-MHz data throughput rate. This translates into an effective computational rate of 1.2 billion multiplications (and a similar number of additions) per second. The chip is reconfigurable for one- and two-dimensional filtering, the total device count is 240000 transistors, and the die size is 1.4 cm*1.4 cm. Tap design, data-flow organization, and clock distribution are discussed.<<ETX>>