Adwin H. Timmer

Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores

Application domain specific DSP cores are becoming increasingly popular due to their advantageous trade-off between flexibility and cost. However, existing code generation methods are hampered by the combination of tight timing and resource constraints, imposed by the throughput requirements of DSP algorithms together with a fixed core architecture. In this paper, we present a method to model resource and instruction set conflicts uniformly and statically before scheduling. With the model we exploit the combination of all possible constraints, instead of being hampered by them. The approach results in an exact and run time efficient method to solve the instruction scheduling problem, which is illustrated by real life examples.

Execution interval analysis under resource constraints

Execution intervals are commonly used in high-level synthesis systems to identify the relation between operations and the cycle steps in which they possibly can be scheduled. These intervals are normally based on the ASAP (as soon as possible) and ALAP (as late as possible) values of operations under the assumption of unlimited resources. In this paper a novel and much more accurate execution interval analysis is presented for designs on which resource constraints are imposed. The analysis prunes the search space of schedulers without limiting the solution space and therefore enhances the quality of schedulers. The method is based on a bipartite graph matching formulation and runs in polynomial time. Well-known benchmarks show the positive effects of the approach on scheduling results and run times.

Module selection and scheduling using unrestricted libraries

Most high-level synthesis schedulers are capable only of mapping an operation to one specific module type. To ensure a full design space exploration, a synthesis system should however select freely from a library containing modules with a large variety in delay, area and so on. A module selection and scheduling approach which allows the full use of such unrestricted libraries is presented. Extensive benchmark results show very fast running times and optimal solutions. This approach clearly illustrates the advantages of synthesis tools which can fully cope with unrestricted libraries, as they lead to designs with less module area.<<ETX>>

Exact scheduling strategies based on bipartite graph matching

Scheduling is one of the central tasks in high-level synthesis. In recent publications a bipartite graph matching formulation has been introduced to prune the search space of schedulers. In this paper, we improve that formulation and introduce two novel aspects related to the way the search space is traversed, namely problem formulation and bottleneck identification. The approach results in a very run time efficient branch-and-bound scheduler searching for a correct ordering of operations from which a schedule can be derived in linear time. The results show that the use of these bipartite graph matching strategies leads to the most run time efficient exact scheduler to date.<<ETX>>

Efficient code generation for in-house DSP-cores

A balance between efficiency and flexibility is obtained by developing a relative large number of in-house DSP-cores each for a relatively small application area. These cores are programmed using existing ASIC synthesis tools which are modified for this purpose. The key problem is to model conflicts arising from the instruction set. A class of instruction sets is defined for which conflicts can be modelled statically before scheduling. The approach is illustrated with a real life example.<<ETX>>

Constraint analysis for DSP code generation

Code generation methods for digital signal processing (DSP) applications are hampered by the combination of tight timing constraints imposed by the performance requirements of DSP algorithms and resource constraints imposed by a hardware architecture. In this paper, we present a method for register binding and instruction scheduling based on the exploitation and analysis of the combination of resource and timing constraints. The analysis identifies implicit sequencing relations between operations in addition to the preceding constraints. Without the explicit modeling of these sequencing constraints, a scheduler is often not capable of finding a solution that satisfies the timing and resource constraints. The presented approach results in an efficient method to obtain high-quality instruction schedules with low register requirements.

NEAT: an object oriented high-level synthesis interface

In this paper a flexible interface to high-level synthesis data (NEAT) is presented. NEAT offers three design views to common high-level synthesis data domains. Inter- and intra-domain relations are used to represent design relations between synthesis objects and to store synthesis results. To extend the functionality of the common synthesis interface programmers use object oriented programming techniques to create their own specific synthesis interface. Interaction between high-level synthesis tools is achieved by exchanging data using a common file-format, which can easily be extended. A graphical interface has been established to allow interactive interpretation and manipulation of synthesis results. NEAT offers unlimited extendibility and no restrictions towards synthesis trajectories, and therefore is highly suitable as a research platform.<<ETX>>