Jochen A. G. Jess

Statistical timing for parametric yield prediction of digital integrated circuits

Uncertainty in circuit performance due to manufacturing and environmental variations is increasing with each new generation of technology. It is therefore important to predict the performance of a chip as a probabilistic quantity. This paper proposes three novel path-based algorithms for statistical timing analysis and parametric yield prediction of digital integrated circuits. The methods have been implemented in the context of the EinsTimer static timing analyzer. The three methods are complementary in that they are designed to target different process variation conditions that occur in practice. Numerical results are presented to study the strengths and weaknesses of these complementary approaches. Timing analysis results in the face of statistical temperature and Vdd variations are presented on an industrial ASIC part on which a bounded timing methodology leads to surprisingly wrong results

Analysis and reduction of glitches in synchronous networks

The influence of transition activity on dynamic power dissipation is analysed by examining three components: dissipation in combinational logic, flipflops and clock line. Transition activity is analysed by making a distinction between useful transitions and glitches (useless transitions). A transition counting and parity evaluation method is used for this. Most glitches can be eliminated by introducing flipflops using retiming and pipelining and/or by choosing different architectures. In this way an optimal level for pipelining can be found.<<ETX>>

Technology mapping for standard-cell generators

A novel approach to technology mapping that produces a standard-cell IC implementation from a previously optimized and decomposed set of Boolean functions is presented. Instead of trying to solve the problem for random libraries of standard cells, which proved to be very difficult, it has been solved for cell generators, which are only limited by technology constraints. The completeness of the sets of cells that can be generated by a cell generator, given a certain technology, makes it possible to use an elegant mapping algorithm. The algorithm was coded in CommonLISP, and used to map a large number of benchmark examples. The results compare favorably with published results.<<ETX>>

High-level synthesis scheduling and allocation using genetic algorithms

In this article a scheduling method is presented which is capable of allocating supplementary resources during scheduling. This makes it very suitable in synthesis strategies based on lower bound estimations techniques. The method is based on genetic algorithms. Special coding techniques and analysis methods are used to improve the runtime and quality of the results. The scheduler can easily be extended to cover other architectural issues and (for example) provides ways to make trade-offs between functional unit allocation and register allocation. Experiments and comparisons show high quality results and fast run times that outperform results produced by other heuristic scheduling methods.

Conflict Modelling and Instruction Scheduling in Code Generation for In-House DSP Cores

Application domain specific DSP cores are becoming increasingly popular due to their advantageous trade-off between flexibility and cost. However, existing code generation methods are hampered by the combination of tight timing and resource constraints, imposed by the throughput requirements of DSP algorithms together with a fixed core architecture. In this paper, we present a method to model resource and instruction set conflicts uniformly and statically before scheduling. With the model we exploit the combination of all possible constraints, instead of being hampered by them. The approach results in an exact and run time efficient method to solve the instruction scheduling problem, which is illustrated by real life examples.

Execution interval analysis under resource constraints

Execution intervals are commonly used in high-level synthesis systems to identify the relation between operations and the cycle steps in which they possibly can be scheduled. These intervals are normally based on the ASAP (as soon as possible) and ALAP (as late as possible) values of operations under the assumption of unlimited resources. In this paper a novel and much more accurate execution interval analysis is presented for designs on which resource constraints are imposed. The analysis prunes the search space of schedulers without limiting the solution space and therefore enhances the quality of schedulers. The method is based on a bipartite graph matching formulation and runs in polynomial time. Well-known benchmarks show the positive effects of the approach on scheduling results and run times.

Probability analysis for CMOS floating gate faults

The electrical behavior of a floating gate MOS transistor is mask-topology-dependent, i.e. floating on different sites of interconnection may result in different fault behavior. In this paper, we present a net-oriented deterministic approach to compute the probability of different open faults on each net, by taking into account the process defect statistics and mask layout data. The open faults causing floating gates are classified into three types, i.e. (1) open causes floating gates of p-channel transistors, (2) open causes floating gates of n-channel transistors, and (3) open causes floating gates of both p-channel transistors and n-channel transistors. For each net the probabilities of floating gate faults (1), (2) and (3) are obtained. The results of the analysis can be used as guidelines for designing more reliable and testable circuits, adopting more accurate fault models, introducing effective testing strategies.<<ETX>>

Foreground memory management in data path synthesis

The management of foreground memory is a main issue in data path synthesis. the storage of values in registers and register files not only determines the number of each of them but also has a major impact on the interconnect structure. Both the amount of multiplexing and interconnect are crucial factors to both the delay and area of a circuit. In this paper it is shown that when values are grouped into register files before being assigned to actual registers, significant savings (20 per cent) can be obtained in the number of local interconnections and the amount of global interconnect at the expense of only slightly more register area. These results can be enhanced by splitting the read and write phases of registers and even more by introducing serial (re)write operations for the same value. the value grouping is based on edge-colouring algorithms that provide a sharp upper bound on the number of register groups needed. After value grouping, the registers are allocated for each register file separately. Algorithms for register allocation published up till now have only considered loop-free data flow graphs. When these algorithms are applied to data flow graphs with loops, unnecessary register transfer operations can be introduced. In this paper a new algorithm is presented that performs a minimal register allocation eliminating all superfluous register transfer operations. Experiments on a benchmark set have shown that in all cases all register transfers could be eliminated at no increase in register cost. This paper provides a deeper insight to the computational complexity of some problems in the area of data path synthesis. It shows that the various subtasks can be solved exactly using polynomial time algorithms.

Stream communication between real-time tasks in a high-performance multiprocessor

The demands in terms of processing performance, communication bandwidth and real-time throughput of many multimedia applications are much higher than todays processing architectures can deliver. The PROPHID heterogeneous multiprocessor architecture template aims to bridge this gap. The template contains a general purpose processor connected to a central bus, as well as several high-performance application domain specific processors. A high-throughput communication network is used to meet the high bandwidth requirements between these processors. In this network multiple time-division-multiplexed data streams are transferred over several parallel physical channels. This paper presents a method for guaranteeing the throughput for hard-real-time streams in such a network. At compile time sufficient bandwidth is assigned to these streams. The assignment can be determined in polynomial time. Remaining bandwidth is assigned to soft-real-time streams at run time. We thus achieve efficient stream communication with guaranteed performance.

Module selection and scheduling using unrestricted libraries

Most high-level synthesis schedulers are capable only of mapping an operation to one specific module type. To ensure a full design space exploration, a synthesis system should however select freely from a library containing modules with a large variety in delay, area and so on. A module selection and scheduling approach which allows the full use of such unrestricted libraries is presented. Extensive benchmark results show very fast running times and optimal solutions. This approach clearly illustrates the advantages of synthesis tools which can fully cope with unrestricted libraries, as they lead to designs with less module area.<<ETX>>