Agnes A. Mewe

Crystalline silicon interconnected strips (XIS): Introduction to a new, integrated device and module concept

A new device concept for high efficiency, low cost, wafer based silicon solar cells is introduced. To significantly lower the costs of Si photovoltaics, high efficiencies and large reductions of metals and silicon costs are required. To enable this, the device architecture was adapted into low current devices by applying thin silicon strips, to which a special high efficiency back-contact heterojunction cell design was applied. Standard industrial production processes can be used for our fully integrated cell and module design, with a cost reduction potential below 0.5 €/Wp. First devices have been realized demonstrating the principle of a series connected back contact hybrid silicon heterojunction module concept.

XIS: A low-current, high-voltage back-junction back-contact photovoltaic device

In this paper we present a low-current, highvoltage back-junction back-contact integrated photovoltaic concept and experimental results of such a device, consisting of strip cells: narrow solar cells instead of conventional square cells. The concept is demonstrated by the successful transformation of a completely finished IBC cell into a XIS (Crystalline Silicon Interconnected Strips) device, leading to a Voc of 8.5 V for a series connection of 14 strip cells. For cell separation, different grooving methods were evaluated with respect to their effect on the quality of the groove surface. The effect of the surface passivation in the grooves, which is regarded as a critical parameter, on the XIS device was simulated to gain a better understanding of the processing requirements.

Improved performance of uncapped Al 2 O 3 and local firing-through Al-BSF in Bi-facial solar cells

Silicon solar cells that dominate todays market are H-pattern cells based on p-type silicon wafer material with a full Al Back Surface Field (BSF) as rear contact. ECNs rear passivated bi-facial PASHA (Passivated on all sides H- pattern) and ASPIRe (All Sides Passivated and Interconnected at the Rear, MWT) concepts answer the market pressure to decrease the euro/watt price and increase the efficiency. For optimized cells we estimate 0.5-0.8% absolute higher cell efficiencies compared to the industrial standard due to better rear passivation and reflection, while thinner wafers <;150um) can be processed with limited yield loss. In addition, Al paste consumption can be reduced by 50-70% owing to the open rear metallization. Here we report on the improved performance of PASHA cells passivated by an uncapped Al2O3 layer on the rear, through which Al paste is fired for contact and local aluminum BSF formation. The Al2O3 dielectric layer is deposited in the Levitrack, an industrial-type system for high-throughput Atomic Layer Deposition (ALD) developed by Levitech. On Cz and mc material, a gain in JscxVoc of 1% and 2.5% respectively is obtained compared to the reference, at a rear metal fraction of 30%. Localized IQE mapping shows that the passivation quality of the Al2O3 passivation layer is maintained after firing which is a major improvement as compared to our previous report. Furthermore, reliability tests on single cell laminates (Cz cells) suggest that the passivation layer remains stable during the lifetime of a module.

Full wafer size IBC cell with polysilicon passivating contacts

We investigate the application of polysilicon carrier-selective passivating contacts to IBC cells. We optimized the passivation of n-type and p-type polysilicon layers by managing the hydrogen supply to the interfacial oxide. Both surface passivation and firing stability were addressed. The best results so far are obtained for passivation capping layers that contain Al2O3 and SiNx. For these passivated polysilicon layers, we present excellent J0 and implied Voc values on textured n-Cz wafers, with best values of < 1 fA/cm2 and 741 mV for n-type, and 10 fA/cm2 and 720 mV for p-type polysilicon, which are maintained after firing. The polysilicon layers were applied as carrier-selective passivating contacts for a full wafer size (156x156 mm2) IBC cell, using industrial compatible processes and commercially available n-type Cz wafers. The implied Voc on the cell reaches 725 mV, which enables IBC cell efficiencies of 24%. After metallization, Voc values of close to 700 mV were obtained.

Designing IBC cells with FFE: Long range effects with circuit simulation

IBC cells with Front Floating Emitter (FFE) pose different design challenges compared to more conventional IBC cells with FSF (Front Surface Field). The FFE enables hole transport over distances that are large compared to the typical BSF or emitter width. The core of the cell design is commonly a device simulation in which, because of the computer resources involved, typically one simulates an as small as possible, but representative part of the solar cell. In an IBC cell this corresponds to 1/2 of the BSF and 1/2 of the emitter. Such a unit cell does not account for important geometric features, such as busbars and pads, edges or interruptions in metallization fingers. We show how to construct an equivalent circuit for our Mercury FFE IBC cells to model features beyond the unit cell efficiently, taking into account the lateral hole transport in the FFE. We compare and calibrate the circuit model against device simulations with quokka.

17.0% Aperture Area Module Efficiency Using Large mc-Si Metal-Wrap-Through Cells

An integrated cell and module technology based on metal-wrap-through (MWT) cells has been developed and demonstrated. 243 cm2 large and 160 µm thin multicrystalline silicon MWT cells were made with a best cell efficiency of 17.9%. From 36 cells with an average efficiency of 17.8% a full-size module was made with an efficiency of 17.0% (aperture area). The module was made using a conductive rear-side foil with conductive adhesive for the interconnection. The module was constructed using a dedicated module manufacturing line that is designed to be able to work with extremely thin cells and provide a high through-put of one 60 cell module per minute.