Agostino Pirovano

Electronic switching in phase-change memories

A detailed investigation of electronic switching in chalcogenide-based phase-change memory devices is presented. An original bandgap model consistent with the microscopic structure of both crystalline and amorphous chalcogenide is described, and a physical picture of the switching mechanism is proposed. Numerical simulations provide, for the first time, a quantitative description of the peculiar current-voltage curve of a Ge/sub 2/Sb/sub 2/Te/sub 5/ resistor, in good agreement with measurements performed on test devices.

Novel /spl mu/trench phase-change memory cell for embedded and stand-alone non-volatile memory applications

A novel cell structure for chalcogenide-based non-volatile Phase-Change Memories is presented. The new /spl mu/trench approach is fully compatible with an advanced CMOS technology, is highly manufacturable and allows to optimize array density and cell performance. Programming currents of 600 /spl mu/A, endurance of 10/sup 11/ programming cycles and data retention capabilities for 10 years at 110/spl deg/C have been demonstrated. The manufacturability is proven by experimental results from multi-megabit arrays.

Reliability study of phase-change nonvolatile memories

A detailed investigation of the reliability aspects in nonvolatile phase-change memories (PCM) is presented, covering the basic aspects related to high density array NVM, i.e., data retention, endurance, program and read disturbs. The data retention capabilities and the endurance characteristics of single PCM cells are analyzed, showing that data can be stored for 10 years at 110/spl deg/C and that a resistance difference of two order of magnitude between the cell states can be maintained for more than 10/sup 11/ programming cycles. The main mechanisms responsible for instabilities just before failure as well as for final device breakdown are also discussed. Finally, the impact of read and program disturbs are clearly assessed, showing with experimental data and simulated results that the crystallization induced during the cell read out and the thermal cross-talk due to adjacent bits programming do not affect the retention capabilities of the PCM cells.

Low-field amorphous state resistance and threshold voltage drift in chalcogenide materials

A detailed investigation of the time evolution for the low-field resistance R/sub off/ and the threshold voltage V/sub th/ in chalcogenide-based phase-change memory devices is presented. It is observed that both R/sub off/ and V/sub th/ increase and become stable with time and temperature, thus improving the cell readout window. Relying on a microscopic model, the drift of R/sub off/ and V/sub th/ is linked to the dynamic of the intrinsic traps typical of amorphous chalcogenides, thus providing for the first time a unified framework for the comprehension of chalcogenide materials transient behavior.

Scaling analysis of phase-change memory technology

The scaling capability of chalcogenide-based phase-change memory (PCM) is discussed. Experimental and numerical results are presented, showing that the reset current scales down with the device contact area, reaching values as low as 50 /spl mu/A. The impact of thermal cross-talk between adjacent bits is investigated, showing that thermal disturbs will not limit the scaling of PCM down to the 65 nm technology node. Finally, scaling rules for the PCM technology are provided.

4-Mb MOSFET-selected phase-change memory experimental chip

This paper presents a 4-Mb phase-change memory experimental chip using an MOS transistor as a cell selector. A cascode bit-line biasing scheme allows read and write voltages to be fed to the storage element with adequate accuracy. The chip was integrated with 3-V 0.18-/spl mu/m CMOS technology and experimentally evaluated. A read access time of 45 ns was measured together with a write throughput of 5 MB/s, which represents an improved performance as compared to present NOR Flash memories. Cell current distributions on the 4-Mb array proved chip functionality and a good working window, thus demonstrating the feasibility of a stand-alone phase-change memory with standard CMOS fabrication process.

A 90nm Phase Change Memory Technology for Stand-Alone Non-Volatile Memory Applications

A 90nm technology node phase change memory (PCM) process, based on a chalcogenide material storage element with a vertical pnp bipolar junction transistor (BJT) selector device, is presented. The small cell area of 12F2, the good electrical results, and the intrinsic reliability demonstrate the viability of the PCM cell concept. Programming currents as low as 400muA, very good distributional data achieved on multi-megabit arrays for programming (set and reset), endurance, and retention, demonstrate the suitability of PCM for fabrication of a high density array at 90nm

Threshold switching and phase transition numerical models for phase change memory simulations

A comprehensive numerical model for chalcogenide glasses is presented, coupling a physically based electrical model able to reproduce the threshold switching with a local nucleation and growth algorithm to account for the phase transition dynamics. The main ingredients of the chalcogenide physics are reviewed and analyzed through simplified analytical models, providing a deeper insight on the origin of the threshold switching mechanism in chalcogenide glasses. A semiconductorlike three-dimensional full-coupled numerical implementation of the proposed model is finally presented and its capabilities to quantitatively reproduce the key elements of the Ge2Sb2Te5 chalcogenide physics are demonstrated in the framework of phase change memory device simulations.

An 8Mb demonstrator for high-density 1.8V Phase-Change Memories

An 8Mb Non-Volatile Memory Demonstrator incorporating a novel 0.32 /spl mu/m/sup 2/ Phase-Change Memory (PCM) cell using a Bipolar Junction Transistor (BJT) as selector and integrated into a 3V 0.18 /spl mu/m CMOS technology is presented. Realistically large 4Mb tiles with a voltage regulation scheme that allows fast bitline precharge and sense are proposed. An innovative approach that minimizes the array leakage has been used to verify the feasibility of high-density PCM memories with improved Read/Write performance compared to Flash. Finally, cells distributions and first endurance measurements demonstrate the chip functionality and a good working window.

Analysis of phase distribution in phase-change nonvolatile memories

The phase transformation in chalcogenide-based nonvolatile memories is studied by cell electrical characterization. The cell state (amorphous, crystalline, or mixed) is changed by applying electrical pulses, then the cell resistance R and the current-voltage characteristics are measured. From the analysis of the electrical parameters of the cell, we provide evidence for a stacked-like phase distribution in the active layer. Results are discussed with reference to the thermal profile during the program pulse in the chalcogenide layer.