Augusto Benvenuti

Electronic switching in phase-change memories

A detailed investigation of electronic switching in chalcogenide-based phase-change memory devices is presented. An original bandgap model consistent with the microscopic structure of both crystalline and amorphous chalcogenide is described, and a physical picture of the switching mechanism is proposed. Numerical simulations provide, for the first time, a quantitative description of the peculiar current-voltage curve of a Ge/sub 2/Sb/sub 2/Te/sub 5/ resistor, in good agreement with measurements performed on test devices.

Low-field amorphous state resistance and threshold voltage drift in chalcogenide materials

A detailed investigation of the time evolution for the low-field resistance R/sub off/ and the threshold voltage V/sub th/ in chalcogenide-based phase-change memory devices is presented. It is observed that both R/sub off/ and V/sub th/ increase and become stable with time and temperature, thus improving the cell readout window. Relying on a microscopic model, the drift of R/sub off/ and V/sub th/ is linked to the dynamic of the intrinsic traps typical of amorphous chalcogenides, thus providing for the first time a unified framework for the comprehension of chalcogenide materials transient behavior.

Self-consistent 2-D model for quantum effects in n-MOS transistors

We present a self-consistent two-dimensional (2-D) model for carrier quantization effects in the channel of highly-doped n-MOSFETs. Quantization is taken into account inside a box region surrounding the inversion channel. The proposed approach extends previously proposed one-dimensional (1-D) schemes allowing one to estimate the quantum mechanical (QM) effects on the device current. Good convergence properties are achieved exploiting the effective intrinsic density concept. The simulator has been applied to MOS devices with different peak channel doping, resulting in an improved description of the device behavior.

A Phase Change Memory Compact Model for Multilevel Applications

In this letter, we show a compact model that describes the main electrical features of phase change memory (PCM) devices. The model coherently reproduces the behavior of both SET and RESET states with the description of the physics of involved phenomena for different bias and temperature conditions. For arbitrary programming pulses, the model is able to generate intermediate states with mixed phase distributions and, thus, with resistance values between the SET and RESET ones. The proposed model is therefore a precious tool for the design of multilevel PCM applications.

Comparative Simulation Study of the Different Sources of Statistical Variability in Contemporary Floating-Gate Nonvolatile Memory

For the first time, a comprehensive comparative study of the impact of different sources of statistical variability in nonvolatile memory (NVM) has been carried out using the 3-D numerical simulation of large statistical ensembles and approaches based on the impedance-field method. Results of the threshold voltage variability in a template 32-nm floating-gate NVM subject to random discrete dopants (RDD), line edge roughness, oxide thickness fluctuations, polysilicon granularity, and interface trapped charge (ITC) are presented. The relative impact of each source of statistical variability has been highlighted, with RDD being identified as the dominant source and ITC as the next most dominant source. Based on the simulation of statistical samples of 1000 microscopically different devices, the shape and spread of the statistical distribution associated with each individual and combined sources of variability have been found to significantly be different from a normal distribution, particularly within the tails that may have significant implications for design and yield. Finally, an ensemble of 59 000 devices is used to characterize the combined impact of all sources of variability.

Quantum-mechanical 2D simulation of surface- and buried-channel p-MOS

A two-dimensional MOS device simulator including quantum-mechanical effects has been developed and applied to surface- and buried-channel p-MOS devices. The Schrodinger equation is solved, retaining a large number of eigenstates, which are then used to build a modified classical distribution accounting for the high energy part of the distribution. With this approach, discontinuities in the gate capacitance near flat bands have been eliminated without introducing any empirical parameter. For accurate device simulation, experimental data on the hole mobility were collected, and a nonlocal mobility model was used for carriers in the bound levels. A standard mobility model is adopted instead for the classically-distributed carriers. Results are presented for the gate capacitance and drain current of 0.35 /spl mu/m p-MOSFET devices, showing a good agreement over a wide range of channel doping concentrations.

Analytical model of deeply-scaled thyristors for memory applications

In this paper we propose an analytical model for the static operation of thyristor, aiming at clarifying the basic physics involved in the switching from the low-conductance to the high-conductance state of the device. Modeling results are compared to TCAD numerical simulations, showing that the analytical calculations can nicely reproduce the main features of the current-voltage device characteristics.

MOSFET simulation with quantum effects and nonlocal mobility model

We present a state-of-the-art two-dimensional (2-D) device simulator suitable for highly doped n-MOSFETs. Quantization effects in the inversion channel are accounted for by a self-consistent solution of the Poisson, current-continuity and Schrodinger equations. The electron charge is given by a density of electrons in the bounded levels plus a density of classically-distributed carriers. Consequently, different mobility models are used. For the former, we adopted a nonlocal, newly-developed mobility model, thus overcoming the deficiency of currently-used mobility models in the high-doping limit. We instead retained a standard local model for the classical regime. Results of the simulations are in good agreement with the experiments.

Working Principles of a DRAM Cell Based on Gated-Thyristor Bistability

This letter discusses the working principles of a memory cell exploiting the bistability of a single nanoscale gated-thyristor to achieve high-performance DRAM operation (T-RAM cell). The device relies on the possibility to reach either of the two stable states of the thyristor by means of a fast low-to-high gate switch and depending on the amount of holes in the gated p-base. In particular, with proper selection of the low and high gate levels, the stationary hole concentration in the p-base leads the thyristor to its high current state while hole depletion results in an orders-of-magnitude lower anode current. This opens the possibility for a DRAM technology with a simple back-end process and fast WRITE and READ operations with low voltage requirements.

Dynamic Analysis of Current-Voltage Characteristics of Nanoscale Gated-Thyristors

This letter presents a detailed experimental investigation of the current-voltage characteristics of deca-nanometer gated-thyristors, highlighting that strong differences exist between the static and the dynamic operation of these devices. In particular, results reveal that the forward-breakover voltage determining thyristor turn-on does not depend only on the applied gate voltage, but also on the rise time of the applied gate pulse, decreasing for fast pulse fronts. This is explained in terms of a higher electron injection from the cathode to the anode triggering device turn-on when the gate switching time is shorter than that required for holes to leave the p-base.