Ahmad H. Kharaz

A study of modeling and simulation for interleaved buck converter

This paper focuses on modeling, analysis and simulation of a 42V/14V dc/dc converter based architecture. This architecture is considered to be a technically viable solution for automotive dual-voltage power system in passenger cars of the near future. An interleaved dc/dc converter system is chosen for the automotive converter topology due to its advantages regarding filter reduction, dynamic response, and power management. Presented herein, is a model based on one kilowatt interleaved six-phase buck converter designed to operate in a Discontinuous Conduction Mode (DCM). The control strategy of the converter is based on a voltage-mode-controlled Pulse Width Modulation (PWM) with a Proportional-Integral-Derivative (PID). The effectiveness of the interleaved step-down converter is verified through simulation using control-oriented simulator, MatLab/Simulink.

Sub-Optimum Detection Scheme for Distributed Closed-Loop Quasi Orthogonal Space Time Block Coding in Asynchronous Cooperative Two Dual-Antenna Relay Networks

In this paper, a sub-optimum detection scheme is proposed for distributed closed-loop quasi orthogonal space time block (D-CL QO-STBC) for two dual antenna relay nodes in decode-and-forward (DF) asynchronous cooperative relay network. The direct transmission (DT) link connection among the source node and the destination node is considered in this network. The proposed scheme is robust against synchronization error and it reduces the receiver complexity as compared to previous work. Furthermore, the maximum available cooperative diversity gain and full transmission rate between the relay nodes and the destination node, and symbol-by-symbol decoding are all achieved. Simulation results are demonstrated to show the proposed scheme for various synchronization errors and effectively eliminate the interference components induced by intersymbol interference (ISI) among the relay nodes.

A practical approach to differential power analysis using PIC micrcontroller based embedded system

Differential power analysis attacks are a major concern to the embedded systems security designers. The attacks can be successful even without knowing much information about the system. The attacks process is initiated by measuring the power consumption of the device followed by establishing a hypothetical power consumption then comparing it with the measured power consumption to extractthe secret information contained in a chip or system. This paper provides the practical realization of such attacks on the Advanced Encryption Standard (AES) implemented on a PIC based system. This includes the experimental setup used for power measurements and the implementation of AES algorithm. The captured power traces are further analyzed in Matlab to reveal the secret key information.

Interleaved Boost DC-DC Converter Using Delta-Sigma Modulation Suitable for Renewable Energy Applications

 Abstract—It is generally accepted that interleaving techniques are efficient at reducing the input/output ripples and increasing the power output of boost converters operating in critical conduction mode.Pulse width modulation (PWM) is used to produce the switching pattern. But this technique causes large switching noise peaks at a multiple number of the carrierfrequency. This paper proposes Interleaved Boost DC- DC suitablefor renewable energy applications. The proposed converterutilizes delta-sigma modulation to control pulse generator. A thorough and effective analysis of the converter is carried out in order to achieve the system stability and to improve the dynamic performance. The output response obtained by this method is very much improved compared to the conventional PWM method of control. Simulation results are provided to illustrate the advantages of the proposed converter and controller scheme. All the advantages of interleaving, such as higher efficiency and reduced ripple for voltage/current, are also achieved in the proposed converter.

Towards an Efficacious Storage Performance in Virtualised Environment

Server virtualisation has dramatically reshaped the information technology industry in recent years. There are too many variants to consider. This paper proposes a practical method of achieving efficacious disk performance in a virtualized environment. Remote disk access in a virtualized environment is emerging as one of the mainstream network intensive applications, with large demands for disk and network bandwidth. As a performance metric we investigate the efficiency and effectiveness of using multi controllers combined with disk alignments. We investigate on how to deliver optimized storage input/output performance and availability at the lowest possible cost and present best practices that we demonstrated on our implementation of VSphere based Oracle installations. We also propose mechanisms to prevent common performance issues like interface queue saturation. Our findings suggest that an underutilized storage system can mask environment misconfigurations. Once the storage system becomes busier, these misconfigurations can cause performance issues. Similarly, storage performance issues are rarely due to a single cause, for example, we had virtual machine misalignment and background process contention. We also concluded that when we use mixed disk technologies in the same storage area network and stress one type with writes, this can also have a negative impact on the others due to the load on the storage controller. In addition to this, we also found that misalignment affects write latency more than the read operations.

Performance comparison between PWM and SSDM techniques in interleaved boost converter

It is generally accepted that interleaving techniques are efficient at reducing the input/output ripples and increasing the power output of boost converters operating in critical conduction mode. This paper gives performance comparison between two famous techniques used to drive power switches; pulse width modulation (PWM) and simplified sigma delta modulation (SSDM). The control strategy of the first converter is based on a voltage mode-controlled Pulse Width Modulation (PWM) with a Proportional-Integral-Derivative (PID) controller. Pulse width modulation (PWM) is used to produce the switching pattern. But this technique causes large switching noise peaks at a multiple number of the carrier frequency. The second converter is use SSDM control loop, the output response obtained by this method is very much improved compared to the conventional PWM method of control. Simulation results are provided to illustrate the advantages of the SSDM method and controller scheme. All the advantages of interleaving, such as higher efficiency and reduced ripple for voltage/current, are also achieved.

An efficient adaptive voltage scaling using delay monitor unit

Low power consumption along with better performance has become an important aspect of processor and system design. Low power system design involves reducing power consumption at both component and system levels subject to constraints imposed by the system performance. Many techniques ranging from architectural to system level are available. Among all techniques, voltage scaling is the most effective. In this paper, an adaptive voltage scaling (AVS) technique using delay monitoring unit along with a closed loop control buck converter is presented. The proposed technique scales down the operating voltage based on a timing error provided by a delay monitor unit which predicts the critical path delay before it happens. Based on that, the controller issues a command to set the output of the closed loop buck converter. The buck converter consists of an Analogue to Digital Converter (ADC), a Pulse Width Modulation (PWM) and a Digital compensator. A complete model of the system has been developed using Matlab/Simulink. The system is simulated over a frequency range of 2.7 to 3.6 GHz corresponding to a regulated voltage range of 0.6 to 1.2 V and achieved 21% power savings compared to the system without the AVS technique.

Impact of loads on power flow in power systems using PowerApps and ETAP

This paper presents a study of the impact of loads on power flow in power system. It deals with the impact of both the voltage nodes and the transmission of active and reactive power in lines, and therefore the loss of active and reactive power in the system. Flexible Alternating Current Transmission System (FACTS) devices are found to be encouraging in improving voltage stability limit in power systems. This paper investigates the application of FACTS devices (Static Var Compensator, SVC) on a 9-bus multimachine power system, it deal with the line losses and improving voltage stability limit. Amount of increased reactive power generation and line losses are taken as indicators of stressed conditions of a power system. The use of SVC is identified by PowerApps and ETAP software packages. Both software are used for IEEE 9 bus test system and the results obtained are presented and interpreted. Streszczenie. Analizowano wpływ napięć w węzłach i przepływ mocy biernej i czynnej na pracę systemu energetycznego. Artykuł przedstawia badania zastosowania urządzeń FACTS w dziewi1)ęcioszynowym, wielomaszynowym systemie. Wykorzystano oprogramowanie ETAP. Wpływ obciążeń na przepływy mocy w systemie wykorzystującym PowerApps i oprogramowanie ETAP

Development of Automotive DC/DC Converter based Centralised Architecture

This paper presents the technical development, modeling, analysis and simulation of a 42V/14V dc/dc converter based architecture for dual/high voltage automotive electrical power system. It overcomes some of the limitations of traditional automotive electrical power system topology that use 14V power net. The proposed system simulation model composed of a 4kW/42V power generation system buffered by a 36V energy storage battery and a 1kW/14V interleaved six-phase buck converter. The effectiveness of the developed model of the complete dc/dc converter-based centralised system architecture is verified through simulation results using control-oriented simulator, MatLab/Simulink.