Ahmed A. Morgan

Power optimization for application-specific networks-on-chips: A topology-based approach

This paper analyzes the main sources of power consumption in Networks-on-Chip (NoC)-based systems. Analytical power models of global interconnection links are studied at different levels of abstraction. Additionally, power measurement experiments are performed for different types of routers. Based on this study, we propose a new topology-based methodology to optimize the power consumption of complex NoC-based systems at early design phases. The efficiency of the proposed methodology is verified through a case study of an MPEG4 video application. Experimental results show a promising improvement in power consumption (8.55%), average number of hops (10.80%), and number of global links (56.25%) compared to the best known related work.

Power-aware topology optimization for networks-on-chips

The choice of a network topology for a networks- on-chip based application significantly impacts its power consumption. In this paper, we propose a new methodology to reduce the total power consumption of the global router-to-router links by selecting the optimal network topology. The proposed methodology merges three mapping approaches: network partitioning, standard topology mapping, and long-range insertion. Analytical power models for global links are studied at different levels of abstraction. The proposed methodology is validated through a case study. Experimental results show the power consumption improvement compared to related work.

A Topology-based Design Methodology for Networks-on-Chip Applications

The topological structure of interconnection networks plays an important role in the design of Networks-on-Chip based Systems. With an enormous number of regular and irregular topologies, acquiring the optimum network topology for a specific application is one of the most complex design problems. In this paper, we propose a new design methodology to automatically acquire the most adapted topology for a given application. A Matlab-based tool called OptNoC is developed to generate the interconnection network using the proposed methodology. The granularity of the OptNoC library facilitates a tool to explore ten different topologies for each design. The current version of the tool mainly aims at minimizing the interconnection network power consumption by using an exhaustive search mapping technique. As a proof of concept, a case study is discussed to show how OptNoC can improve the interconnection network power consumption compared to other tools.

A reliability-aware design methodology for Networks-on-Chip applications

Network reliability is a key design issue that impacts the performance of all Networks-on-Chip-based systems. In this paper, we develop two reliability models for on-chip interconnection networks using both deterministic and probabilistic measures. Graph-theoretic concepts are adopted with modifications to obtain application-specific reliability models for nine regular network topologies. Using these models, a new methodology is proposed to improve the network reliability of any target application using a topology-based design approach. To validate the effectiveness of the proposed methodology, a case study was performed using an MPEG4 video application. The results were promising and proved that the proposed methodology helps designers better evaluate the impact of their network architecture on the system reliability and assists them in choosing the most appropriate architecture for a target application at early design phases.

Multi-objective optimization for Networks-on-Chip architectures using Genetic Algorithms

Networks-on-Chip (NoC) architecture design faces a trade-off between different conflicting metrics. In this paper, we target one aspect of this trade-off: area versus average delay. The NoC architecture generation is formulated as a two-objective optimization problem and a Genetic Algorithm (GA)-based technique is used to solve it. According to the application requirements and the design constraints, the optimization process could be controlled by the designer by specifying weight factors for area and delay. As a proof of concept, our technique is applied to three real applications with different number of cores. Results show that the proposed solution is a promising way to achieve the best architecture with respect to both area and delay.

Area-aware topology generation for Application-Specific Networks-on-Chip using network partitioning

One of the challenging problems in Application-Specific Networks-on-Chip (ASNoC) design is customizing the topological structure of the on-chip network in order to meet the application requirements with the minimum possible cost. In this paper, the area cost of ASNoCs is reduced by using network partitioning techniques. Given the application core graph, the partitioning problem is formulated as an optimization one. Partitioning results in increasing the average delay, which is compensated for by adjusting the network bandwidth. A methodology is proposed for an area-aware custom topology generation employing network partitioning. As a proof of concept, our methodology is applied to three different applications with different number of cores. Results show that the proposed methodology is a promising way to reduce the ASNoC area compared to other standard and custom topology generation techniques.

Application-specific networks-on-chip topology customization using network partitioning

One of the most challenging problems in Application-Specific Networks-on-Chip (ASNoC) design is to customize the topological structure of the on-chip network in order to meet the application requirements with the minimum possible cost. In this paper, the area cost of ASNoCs is reduced by using network partitioning techniques. The enhancement in area cost is achieved by reducing both routers area and the number of global links. Given the application core graph, Fiduccia-Mattheyses (FM) algorithm is adopted with modification to formulate the partitioning problem as an optimization one. As a proof of concept, our technique is applied to three different applications with different number of cores. Results show that the proposed technique is a promising way to reduce the ASNoC area compared to other topology generation techniques.

Improving Networks-on-Chip performability: A topology-based approach

The performability metric is commonly used in Networks-on-Chip (NoC)-based systems to represent their abilities to successfully complete specific tasks in finite time intervals. In this paper, we present a novel topology-based performability model for NoC-based systems. The model is used to evaluate the performability of NoC-based systems at early design phases. A comparative study of nine commonly used network architectures is performed using the proposed model. The purpose of the study is to explore the impact of the network topology on the performability of NoC-based systems. Using the output from this study, a new methodology is proposed to improve the performability of a given application at early design phases. In this methodology, a joint consideration of five design parameters (network topology, target application traffic distribution, mapping of processing elements, noise power, and voltage swing) is carried out. Using the proposed methodology, designers can select the optimal topology for a given application that maximizes system performability. The effectiveness of the proposed methodology in determining the optimal topology is verified by experimental work and validated through a case study of a video application. Copyright

Multi-objective optimization of NoC standard architectures using Genetic Algorithms

One of the challenging problems in Networks-on-Chip (NoC) design is optimizing the architectural structure of the on-chip network in order to maximize the network performance while minimizing corresponding costs. In this paper, a methodology for multi-objective optimization of NoC standard architectures using Genetic Algorithms is presented. The methodology considers two cost metrics, power and area, and two performance metrics, delay and reliability. Moreover, our methodology combines the best selection of NoC standard topology, the optimum mapping of application cores onto that topology, and the best routing of application traffic traces over the generated network. The methodology is evaluated by applying it to an NoC benchmark application as a case study. Results show that the architectures generated by our methodology outperform those of other standard architectures customization techniques with respect to power, area, delay, reliability, and the combination of the four metrics.

Performance Analysis of Networks-on-Chip Routers

Routers are pivotal modules in networks-on-chip (NoC)-based designs. Therefore, acquiring an accurate estimation of the router performance is an essential parameter at early design phases. In this paper, we explain how queuing analysis could be applied to a NoC-based system to extract desired performance parameters. We focus on the analysis of routers since they are at the heart of any NoC-based system. Because there are several possible NoC architectures, we first show the NoC internal structure and how router design depends on the type of network topology. Next, we discuss different types of router structures that could be used. We used Markov chain analysis to derive an analytical model for an input-queue mesh-based router as a case study. Detailed analysis were carried out on the model simulation results to show its response to the change in different design parameters.