M. Watheq El-Kharashi

Power optimization for application-specific networks-on-chips: A topology-based approach

This paper analyzes the main sources of power consumption in Networks-on-Chip (NoC)-based systems. Analytical power models of global interconnection links are studied at different levels of abstraction. Additionally, power measurement experiments are performed for different types of routers. Based on this study, we propose a new topology-based methodology to optimize the power consumption of complex NoC-based systems at early design phases. The efficiency of the proposed methodology is verified through a case study of an MPEG4 video application. Experimental results show a promising improvement in power consumption (8.55%), average number of hops (10.80%), and number of global links (56.25%) compared to the best known related work.

A fast string search algorithm for deep packet classification

In this paper, we propose a string search algorithm that requires reduced time complexity. It also requires a small amount of memory, and shows better performance than any other algorithm for deep packet classification based on their payload data. The proposed algorithm is based on Boyer-Moore algorithm but requires a much reduced number of operations. In addition, our algorithms memory requirement is lower than Boyer-Moore algorithm without sacrificing its speed. We have done time complexity analysis and verified its time complexities through extensive numerical simulations. These simulations show that our algorithms performance is better for long text, long pattern, and large alphabet set and even its worst case time complexity linearly depends on the length of the text.

A reliability-aware design methodology for Networks-on-Chip applications

Network reliability is a key design issue that impacts the performance of all Networks-on-Chip-based systems. In this paper, we develop two reliability models for on-chip interconnection networks using both deterministic and probabilistic measures. Graph-theoretic concepts are adopted with modifications to obtain application-specific reliability models for nine regular network topologies. Using these models, a new methodology is proposed to improve the network reliability of any target application using a topology-based design approach. To validate the effectiveness of the proposed methodology, a case study was performed using an MPEG4 video application. The results were promising and proved that the proposed methodology helps designers better evaluate the impact of their network architecture on the system reliability and assists them in choosing the most appropriate architecture for a target application at early design phases.

Targeting spam control on middleboxes: Spam detection based on layer-3 e-mail content classification

This paper proposes a spam detection technique, at the packet level (layer 3), based on classification of e-mail contents. Our proposal targets spam control implementations on middleboxes. E-mails are first pre-classified (pre-detected) for spam on a per-packet basis, without the need for reassembly. This, in turn, allows fast e-mail class estimation (spam detection) at receiving e-mail servers to support more effective spam handling on both inbound and outbound (relayed) e-mails. In this paper, the naive Bayes classification technique is adapted to support both pre-classification and fast e-mail class estimation, on a per-packet basis. We focus on evaluating the accuracy of spam detection at layer 3, considering the constraints on processing byte-streams over the network, including packet re-ordering, fragmentation, overlapped bytes, and different packet sizes. Results show that the proposed layer-3 classification technique gives less than 0.5% false positive, which approximately equals the performance attained at layer 7. This shows that classifying e-mails at the packet level could differentiate non-spam from spam with high confidence for a viable spam control implementation on middleboxes.

An FPGA implementation of the flexible triangle search algorithm for block based motion estimation

In this paper a hardware architecture for the implementation of the flexible triangle search algorithm (FTS) using FPGAs is proposed. The FTS is a fast block-matching algorithm for motion estimation proposed in previous work, which can be used for video compression. The FTS finds the best matching blocks between two frames using a search triangle which changes its direction and size through a set of operations. These operations provide the triangle with the necessary flexibility to locate the best matching block. Simulation results indicate that the FTS reduces the number of block matching operations compared with other fast block matching algorithms without affecting quality or compression ratio of the compressed bitstream. In this paper, a hardware architecture for a FPGA implementation of the FTS algorithm is proposed. This architecture is simulated and tested using VHDL and synthesized using Xilinx ISE for the Xilinx Spartan3 device. The results obtained were compared to an FPGA implementation of the full search (FS) algorithm. Results indicates that the FTS FPGA implementation requires less number of gates than FS and the required number of cycles needed to complete motion search for one block is much lower. This indicates that the proposed implementation is fast and requires less hardware and power than existing ones

Multi-objective optimization for Networks-on-Chip architectures using Genetic Algorithms

Networks-on-Chip (NoC) architecture design faces a trade-off between different conflicting metrics. In this paper, we target one aspect of this trade-off: area versus average delay. The NoC architecture generation is formulated as a two-objective optimization problem and a Genetic Algorithm (GA)-based technique is used to solve it. According to the application requirements and the design constraints, the optimization process could be controlled by the designer by specifying weight factors for area and delay. As a proof of concept, our technique is applied to three real applications with different number of cores. Results show that the proposed solution is a promising way to achieve the best architecture with respect to both area and delay.

Binary LNS-based naive Bayes hardware classifier for spam control

We propose a hardware architecture for a naive Bayes classifier in the context of e-mail classification for spam control. Our proposal presents a word-serial naive Bayes classifier architecture that utilizes the logarithmic number system (LNS) to reduce the computational complexity. We present the hardware architecture for non-iterative binary LNS recoding using a look-up table approach. Our design was synthesized targeting an Altera Stratix CPLD device. The synthesized classifier was functionally verified with a MATLAB implementation. Our binary LNS naive Bayes classifier exhibits high e-mail classification throughput of more than 30 thousands e-mails per second

Binary LNS-based naive Bayes inference engine for spam control: noise analysis and FPGA implementation

A hardware architecture for naive Bayes inference engine to classify e-mail contents for spam control is proposed. The inference engine utilises the logarithmic number system (LNS) to simplify naive Bayes computations. For high throughput LNS recoding, a non-iterative binary LNS recoding hardware architecture that uses look-up table approach is proposed. A noise model for the inference engine was developed and the noise bounds were analysed to determine the inference accuracy. The inference engine design is synthesised targeting the Altera Stratix field programmable gate array (FPGA) device. From the synthesis results, the binary LNS naive Bayes inference engine was found to have the capability to classify more than 117 million features per second, given a stream of a priori and likelihood probabilities as input with small computation noise. The synthesised inference engine was functionally verified against a MATLAB implementation.

MPC-On-Chip: An Embedded GPC Coprocessor for Automotive Active Suspension Systems

Safety critical automotive systems require tight real-time constraints. This letter presents a case study for embedded implementation of a model predictive controller (MPC) used to control an automotive active suspension system. It proposes a special purpose coprocessor for solving the online mathematical optimization needed by the controller, while maintaining real-time constraints imposed by system dynamics. Mathematical formulation for the optimum usage of hardware resources is provided and verified for its applicability on a proposed platform.

A High-Speed, Fully-Pipelined VLSI Architecture for Real-Time AES

Nowadays, data encryption and decryption have become mandatory for any real-time communication applications. We propose a novel, area-speed efficient, high-speed architecture for the Advanced Encryption Standard hardware implementation. Our proposed architecture utilizes the composite field technique for SubBytes/InvSubBytes transformation instead of the traditionally-used look up table technique. As a result, the unbreakable delay of using look up tables in the traditional technique is eliminated. This, in turn, enables sub-pipelining implementation for further speeding up. Moreover, composite field arithmetic is employed to reduce the critical path delay. We propose a new algorithm to generate the optimum isomorphic mapping matrix, which reduces the critical path delay dramatically. In addition, an efficient key expansion architecture suitable for real-time applications is presented. Using the proposed architecture, a fully sub-pipelined implementation with 6 sub-stages in each round can achieve a throughput of 49.401 Gbps on a Xilinx XC2V6000FF1152-6 device in non-feedback mode, which is twice faster than the fastest Advanced Encryption Standard FPGA implementation known to date.