Ahmed A. Youssef

Digitally-controlled RF passive attenuator in 65 nm CMOS for mobile TV tuner ICs

A novel VHF/UHF passive attenuator linearization circuit suitable for mobile TV applications has been designed and implemented in 65 nm CMOS technology. The proposed attenuator has a wide gain range of 48 dB that can be digitally programmed in 3 to 6 dB steps. At every gain setting, the input and output of the attenuator are matched to 50 Ω 2 to facilitate its integration into mobile TV tuners.

Low power interference-robust UWB Low Noise Amplifier in 0.18-μm CMOS technology

This paper proposes a very low power low noise amplifier (LNA) operating from 3.1 GHz to 8 GHz for OFDM- UWB systems. The LNA is intended to cover groups 1 and 3 while filtering out group 2, whose spectrum is shared with WLAN signals representing troublesome interference. By utilizing both nMOS and pMOS transistors to boost the transconductance, the LNA draws only 1.5 mA from a 1.5 V supply. The LNA IC has been realized in 0.18 mum CMOS technology from TSMC.

Design Issues for Sensor Network RF Receivers

Low data rate wireless sensor networks are emerging as potential solutions for many valuable applications, ranging from security and industrial control, to wildlife monitoring. This paper addresses some of the major design challenges involved with integrating RF communication functionality in sensor network nodes. Characteristics of the sensor network node design space, including transmitted range, sensitivity, power consumption, and integration are extracted and discussed. Current state-of-the-art low power receivers are examined with respect to the design space presented. Finally, the physical limitations of these receivers when they scale down to the sensor network design space are explored.

Guidelines for the noise optimization of 0.18 /spl mu/m CMOS tuned LNAs

Based on four noise parameters and two-port noise theory, considerations for noise optimization of fully integrated tuned low-noise amplifier (LNA) designs are presented. This paper demonstrates explicit design guidelines for a 0.18 micron CMOS tuned LNA. These guidelines give a useful indication of the design tradeoffs between noise figure, power dissipation and gate overdrive voltage for the LNA designed using this technology.

A sub - 2 dB noise figure wideband LNA in 65 nm CMOS for mobile TV applications

A novel broadband CMOS LNA based on the noise-canceling approach has been designed and implemented in 65 nm CMOS technology. The noise-canceling mechanisms used in this LNA allow the achievement of a noise figure as low as 1.6 dB to be feasible across the VHF/UHF bands without using any inductors. The LNA has a gain greater than 36 dB and consumes only 18 mW of power.

Nanometer CMOS LNAs for Mobile TV Receivers

This chapter presents the design of a wideband low-noise amplifier in 65 nm digital CMOS technology that takes advantage of the noise and distortion cancelling techniques described in Chapter 2. In addition to examining the practicality of these techniques, this chapter also discusses the challenges associated with using a nano-scale technology such as the 65 nm CMOS process, including the MOSFET low output resistance, the high resistivity of the polysilicon material, the increased substrate coupling, and the use of a digital transistor layout that is not optimized for radio frequency (RF) operation. Furthermore, this chapter examines ways to achieve the nonlinearity requirement of the mobile TV application while providing RF gain control in the LNA. Lastly, this chapter looks at biasing techniques that allow the LNA to withstand process and temperature variations, and verifies the design’s performance using lab measurements from tests conducted on a prototype of the designed LNA.

Wide Dynamic Range Mobile TV Front-End Architecture

This chapter presents a design example of a 65 nm CMOS chip that integrates the wide dynamic range DVB-H front-end architecture described in the previous chapter with an RF power level indicator circuit. The front-end consists of the wideband noise-cancelling LNA presented in Chapter 3 and the RF passive attenuator presented in Chapter 4. A power level indicator circuit will provide an automatic gain control function to the mobile TV front-end architecture. The chapter concludes by presenting some experimental results for this test chip.

RF Attenuator Linearization Circuits

This chapter discusses the challenges associated with designing low-power receivers with large dynamic range suitable for use in mobile TV applications. It also proposes techniques to achieve a highly-linear front-end circuit with low noise figure at sensitivity. Such a front-end would be suitable for cellular phone environments that require small, low-cost, low-power components. A silicon prototype of the described solution supported with measurement results is given to demonstrate the concept.

Wideband CMOS LNA Design Techniques

The low-noise amplifier (LNA) is the backbone of any radio frequency (RF) communication receiver. Its specifications define the overall receiver noise performance and can have deleterious effects on the overall linearity. CMOS LNAs specifically receive intense attention because they help in achieving a one-chip solution by integrating the LNA with the receiver’s baseband digital signal processing blocks that are inherently realized in CMOS technology. The one-chip solution reduces overall package cost and form factor. Moreover, it saves the power required to drive package pins in the multi-chip solution [36, 37].

RF architectures in CMOS for the emerging wireless technologies: challenges and opportunities

The recent proliferation of personal communications systems (PCS) applications and cellular phones is driving a demand for portable systems which share the common requirements of low cost, small form factor and low power consumption. In addition, the emergence of various wireless technologies around the world requires that the RF wireless radios (transceivers) can operate in more than one mode. This tutorial will discuss the evolution of the wireless industry and will focus on power technology and transceiver architectures used in modern cost effective integrated mobile communication systems. Architectures and design techniques suitable for multistandard/mode low power transceivers in CMOS technology will be presented. The recent advances and challenges in the mobile industry will be highlighted by examining TV enabled cellular phones and Wireless sensor radios.