James W. Haslett

A Fine Resolution TDC Architecture for Next Generation PET Imaging

A fine resolution and process scalable CMOS time-to-digital converter (TDC) architecture is presented. A 6-bit fine resolution TDC design using the new architecture is evaluated for positron emission tomography (PET) imaging application. The TDC architecture uses a hierarchical delay processing structure to achieve single cycle latency and high speed of operation. The fine resolution converter, realized in 130 nm CMOS, is designed to operate over a reference clock frequency of 500 MHz but can be scaled to multi GHz operation through time interleaving. Without external calibration, the TDC is used as a 5-bit fine resolution converter with 4.65 ENOB (effective number of bits). Under this condition, the 6-bit TDC has an INL (integral non-linearity) measurement of less than 1.45 LSB and a DNL (differential non-linearity) measurement of less than 1.25 LSB. With external calibration, a reduction of more than 50% in INL/DNL nonlinearities is demonstrated improving the ENOB to 5.5 bits, pushing the TDC to a 6-bit fine resolution operation. The TDC has a 31 ps timing resolution and power consumption of less than 1 mW. The design is believed to be the fastest and the lowest power consuming fine resolution TDC in the literature.

Noise figure optimization of inductively degenerated CMOS LNAs with integrated gate inductors

This paper discusses noise figure optimization techniques for inductively degenerated cascode CMOS low-noise amplifiers (LNAs) with on-chip gate inductors. Seven different optimizations techniques are discussed. Of these, five new cases provide power match and balance the transistor noise contribution and the noise contribution from all parasitic resistances in the gate circuit to achieve the best noise performance under the constraints of integrated gate inductor quality factor, power consumption, and gain. Three of the power matched techniques (two power constrained optimizations and a gain-and-power constrained optimization) are recommended as design strategies. These three optimization techniques significantly improve the noise figures for LNA designs that are to employ on-chip gate inductors.

Sub-0.2 dB Noise Figure Wideband Room-Temperature CMOS LNA With Non-50

This paper presents a wideband low-noise amplifier (LNA) designed to be used as the first stage of the receiver in the Square Kilometer Array radio telescope. The LNA design procedure and its layout features are discussed. The noise figure optimization procedure determines the signal-source resistance that results in reduced noise figure. When used in the radio telescope, the required signal-source resistance will be presented by the telescope custom-made antenna elements. The LNA, designed in 90 nm bulk CMOS, achieves sub-0.2 dB noise figure from 800 MHz to 1400 MHz, return loss of more than 11 dB, gain of more than 17 dB driven into a 50 load, output 1 dB compression point of 2 dBm, output IP3 of 12 dBm, and output IP2 of 22 dBm while consuming 43 mA from a 1 V supply. In the LNA implementation presented in this paper the load choke inductor and the source inductor are integrated whereas the gate-, bias-, and the choke-inductor between two transistors of the cascode are external. The noise figure of the presented LNA is to our knowledge the lowest noise figure achieved by a power matched wideband CMOS LNA at room temperature.

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In this article, the large-signal, small-signal, and noise performance of the Cherry-Hooper amplifier with emitter-follower feedback are analyzed from a design perspective. A method for choosing the component values to obtain a low group delay distortion or Bessel transfer function is given. The design theory is illustrated with an implementation of the circuit in a 47-GHz SiGe process. The amplifier has 19.7-dB gain, 13.7-GHz bandwidth, and /spl plusmn/10-ps group delay distortion. The amplifier core consumes 34 mW from a -3.3-V supply.

Signal-Source Impedance

A 40 dB dynamic range, DC-4 GHz parallel-summation logarithmic amplifier is presented in this paper. The amplifier realizes a piecewise approximation to an exact logarithmic response. A design procedure that yields breakpoints on the exact response is described, along with delay-matching networks for parallel-summation logarithmic amplifiers. The amplifier was constructed in a 35 GHz silicon bipolar process, has /spl plusmn/5 dB logarithmic conformity over a DC-4 GHz bandwidth and has rise and fall times of 100 ps. The integrated circuit has dimensions of 2/spl times/2 mm/sup 2/ and consumes 750 mW from a -5 V supply.

Analysis and design of HBT Cherry-Hooper amplifiers with emitter-follower feedback for optical communications

A technique for chopper-stabilizing commercial linearized operational transconductance amplifiers (OTAs) to remove output offset current errors is described. Design equations which illustrate performance tradeoffs as a function of component values are given. The results are verified experimentally using a common bipolar OTA. >

A DC-4-GHz true logarithmic amplifier: theory and implementation

The low-frequency noise in silicon JFETs was measured continuously for temperatures varying from 30 to 300 K. Distinct peaks in the noise were observed for all transistors tested, suggesting the presence of distinct trapping levels in the forbidden gap. An attempt to match theory with experiment indicates that one of the peaks can be explained by the presence of gold in the silicon as expected. However, a discrete trapping level cannot explain the second peak observed in the noise, as unrealistic capture cross sections for the traps would be required. It appears that the mechanism causing this second peak also contributes to the noise level at higher frequencies, and more work must be done to determine the exact nature of the processes involved. A third peak at lower temperatures cannot be explained with present theory. Possible causes of the noise appear to be dislocations in the crystal lattice, gold acceptors, and a splitting of the gold level due to strain.

Chopper-stabilized operational transconductance amplifiers

A tunable transformer-based Q-enhancement method for monolithic inductors used in parallel resonant LC tanks is presented. The Q of the inductor that forms the transformer primary is enhanced by cancelling the voltage drop across the series loss resistance of the primary with a voltage of opposite polarity that is induced by a current in the secondary. The circuit allows DC voltage control of Q-enhancement. Techniques to address stability issues associated with the positive feedback are described. The circuit was fabricated in 0.18 /spl mu/m CMOS and the performance was verified experimentally.

Temperature dependence of low-frequency excess noise in junction-gate FET's

A precision operational amplifier has been developed for instrumentation applications in which the circuitry must operate in ambient temperatures as high as 200/spl deg/C. At 200/spl deg/C the amplifier maintains an input offset voltage and current of less than 200 /spl mu/V and 1 nA respectively, a gain bandwidth product of 2.2 MHz, and a slew rate of 5.4 V//spl mu/S. The amplifier is fabricated in a standard CMOS process and consumes 5.5 mW of power at a supply voltage of 5 V. A continuous time auto-zeroed amplifier topology is used to achieve the low offset voltage levels. At high temperatures the leakage currents of the sample and hold switches used to achieve auto-zeroing, degrading the offset correction voltages stored on the hold capacitors. This degradation is reduced by using large external hold capacitors and by minimizing the diffusion area of the switches through the use of a doughnut shaped layout. The effect of the voltage degradation is reduced by sensing the offset correction voltage with a low sensitivity differential auxiliary input stage. A new input switch topology is used to reduce the amplifiers input offset current at high temperatures. >

Tunable coupled inductor Q-enhancement for parallel resonant LC tanks

A novel 0.13mum CMOS integrated linear voltage to pulse delay time converter (VTC) is proposed. The VTC architecture uses current starved inverters where the inverter delay versus input voltage characteristic is linearized by using several parallel current starving devices with different gate bias voltages and different amounts of source degeneration. The VTC operates at a clock frequency of up to 500 MHz. Input voltage signals of up to 2 GHz can be converted to pulse time delays by using several VTCs in parallel. Since the voltage to time conversion is essentially done with a single inverter stage no sample-and-hold is needed for the input voltage. The VTC can be used in combination with a time-to-digital converter (TDC) to build a simple high speed, low power, time based analog-to-digital converter (ADC) that consumes very little chip area