Ahmed Emira

A pseudo differential complex filter for Bluetooth with frequency tuning

A 12th-order OTA-C complex filter with a nonconventional frequency tuning for a Bluetooth receiver is implemented in a low-cost mainstream 0.35-/spl mu/m CMOS process. This proposed frequency tuning scheme is simpler than the conventional one based on phased-locked loop (PLL). Furthermore, a high-speed pseudo differential OTA using common-mode feedforward (CMFF) and common-mode feedback (CMFB) strategy is proposed. The filter bandwidth is 1 MHz and is centered at 2 MHz. Image and adjacent channels are attenuated by more than 45 and 27 dB, respectively. The integrated input referred noise is 29 /spl mu/V/sub rms/, and the filter chip dissipates 4.7 mA from a 2.7 V supply. The theoretical and experimental results are in good agreement.

Nonlinear Dynamics of Spring Softening and Hardening in Folded-MEMS Comb Drive Resonators

This paper studies analytically and numerically the spring softening and hardening phenomena that occur in electrostatically actuated microelectromechanical systems comb drive resonators utilizing folded suspension beams. An analytical expression for the electrostatic force generated between the combs of the rotor and the stator is derived and takes into account both the transverse and longitudinal capacitances present. After formulating the problem, the resulting stiff differential equations are solved analytically using the method of multiple scales, and a closed-form solution is obtained. Furthermore, the nonlinear boundary value problem that describes the dynamics of inextensional spring beams is solved using straightforward perturbation to obtain the linear and nonlinear spring constants of the beam. The analytical solution is verified numerically using a Matlab/Simulink environment, and the results from both analyses exhibit excellent agreement. Stability analysis based on phase plane trajectory is also presented and fully explains previously reported empirical results that lacked sufficient theoretical description. Finally, the proposed solutions are, once again, verified with previously published measurement results. The closed-form solutions provided are easy to apply and enable predicting the actual behavior of resonators and gyroscopes with similar structures.

CMOS RF receiver system design: a systematic approach

A unified system-level design methodology for highly integrated CMOS radio frequency receiver design is introduced. This complete system-level design methodology is targeted to minimize the total power consumption of the receiver. System-level design techniques which can be used to derive the overall receiver radio specifications and study noise and linearity performance of receivers are presented. Then, a few circuit examples of building blocks in receiver signal chain are analyzed to show a linear relationship between power and dynamic range of the blocks. The result is then used to derive the optimal system specification distribution among receiver signal chain building blocks yielding the minimum total receiver power consumption for a given system performance. The theory and an actual CMOS Bluetooth receiver design are compared showing very good agreement.

A 100-MHz 8-mW ROM-less quadrature direct digital frequency synthesizer

A low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using a ROM look-up table to store the sine values as in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications. To demonstrate the proposed technique, a quadrature DDFS has been implemented using 0.5-/spl mu/m CMOS process and occupies an active area of 1.4 mm/sup 2/. It consumes 8 mW at 100 MHz and operates from a single 2.7-V supply. The spurious-free dynamic range is better than 59 dBc at low synthesized frequencies and the frequency resolution is 1.5 kHz.

Chameleon: a dual-mode 802.11b/Bluetooth receiver system design

In this paper, an approach to map the Bluetooth and 802.11b standards specifications into an architecture and specifications for the building blocks of a dual-mode direct conversion receiver is proposed. The design procedure focuses on optimizing the performance in each operating mode while attaining an efficient dual-standard solution. The impact of the expected receiver nonidealities and the characteristics of each building block are evaluated through bit-error-rate simulations. The proposed receiver design is verified through a fully integrated implementation from low-noise amplifier to analog-to-digital converter using IBM 0.25-/spl mu/m BiCMOS technology. Experimental results from the integrated prototype meet the specifications from both standards and are in good agreement with the target sensitivity.

RF MEMS Fractal Capacitors With High Self-Resonant Frequencies

This letter demonstrates RF microelectromechanical systems (MEMS) fractal capacitors possessing the highest reported self-resonant frequencies (SRFs) in PolyMUMPS to date. Explicitly, measurement results show SRFs beyond 20 GHz. Furthermore, quality factors higher than 4 throughout a band of 1-15 GHz and reaching as high as 28 were achieved. Additional benefits that are readily attainable from implementing fractal capacitors in MEMS are discussed, including suppressing residual stress warping, eliminating the need for etching holes, and reducing parasitics. The latter benefits were acquired without any fabrication intervention.

A low-voltage charge pump for micro scale thermal energy harvesting

For energy harvesting applications, a power management unit (PMU) architecture operating at low input voltages is required. The most critical sub-blocks of such a PMU are the voltage multiplier and the low-voltage clock generator. An ultra-low-voltage exponential gain charge pump (ECP) that serves as a voltage multiplier for such PMUs is analyzed. A low-cost fully-integrated CMOS implementation for the ECP is proposed. Circuit simulations demonstrate a 0.85-0.90V output for input voltages as low as 150mV and static loads up to 1.5µA. The ECP was simulated in Cadence environment using a TSMC CMOS 65nm process and a total of 5nF MIM capacitors.

All-pMOS 50-V Charge Pumps Using Low-Voltage Capacitors

In this paper, two high-voltage charge pumps (CPs) are introduced. In order to minimize the area of the pumping capacitors, which dominates the overall area of the CP, high-density capacitors have been utilized. Nonetheless, these high-density capacitors suffer from low breakdown voltage, which is not compatible with the targeted high-voltage application. To circumvent the breakdown limitation, a special clocking scheme is used to limit the maximum voltage across any pumping capacitor. The two CP circuits were fabricated in a 0.6- μm CMOS technology with poly0-poly1 capacitors. The output voltage of the two CPs reached 42.8 and 51 V, whereas the voltage across any capacitor did not exceed the value of the input voltage. Compared with other designs reported in the literature, the proposed CP provides the highest output voltage, which makes it more suitable for tuning MEMS devices.

A low start up voltage charge pump for thermoelectric energy scavenging

In this paper, an ultra-low-voltage charge pump is presented. Two techniques are used to reduce required number of stages and improve power efficiency, namely clock boosting and Vt cancellation. Clock boosting is employed to increase the output voltage per stage resulting in lower number of stages, and hence smaller output resistance. Vt cancellation is achieved by using an auxiliary circuit that enables the charge pump to operate at input voltages as low as 300mV. Compared to conventional charge pump techniques, the proposed technique is shown to offer higher power efficiency and voltage gain. The charge pump is designed using TSMC 0.25µm CMOS technology.

Variable gain amplifier with offset cancellation

In this paper, the design of variable gain ampli.er (VGA) for wireless receiver applications is presented. The VGA uses ac coupling (highpass filter) for dc offset rejection, while each VGA stage is designed to have constant output offset to overcome the slow response of the highpass filter. Due to the architecture chosen, The VGA has a fairly constant bandwidth in the entire gain range, and therefore it has constant settling time. It has been simulated and laid out using IBM SiGe BiCMOS 0.25Ām process. The VGA is OpAmp-R based and has gain range of -4 → 64dB with 2dB steps. It has about 35MHz bandwidth and consumes 1.5mA from 2.5V supply.