Ahmed Nader Mohieldin

Boost Converter With Dynamic Input Impedance Matching for Energy Harvesting With Multi-Array Thermoelectric Generators

This paper presents a built-in input matching technique capable of handling a wide variation of multi-array thermoelectric generator (TEG) impedances ranging two decades, from 10 s to 1000 s of ohms. Maximum power point tracking (MPPT) control for a boost converter (BC) is introduced. The analytical expressions derived offer insight on the manner in which MPPT interacts with a BC to achieve best performance. The BC operates in a discontinuous conduction mode under pulse frequency modulation to minimize power consumption and maximize efficiency for light loads. Losses are minimized by implementing a pseudo-zero current switching control via the PMOS switch on/off time, and the output voltage is set using a global clocked comparator. A prototype was fabricated in 0.5 μm CMOS where efficiency measurements showed a maximum value of 61.15% for an RTEG = 33.33 Ω, and quiescent power consumption was 1 μW.

A low-noise low-voltage CT /spl Delta//spl Sigma/ modulator with digital compensation of excess loop delay

The implementation of a 3/sup rd/-order 50MS/s CT /spl Delta//spl Sigma/ modulator with 5 levels of quantization, for a CDMA2k receiver, is presented. Its 9nVrms//spl radic/Hz input referred noise produces 80dB of DR in a 600kHz BW for signals as low as 70mVrms. It draws 4mA from a single 1.5V supply, uses a 90nm CMOS process and occupies 0.25mm/sup 2/.

A 1.5-V multi-mode quad-band RF receiver for GSM/EDGE/CDMA2K in 90-nm digital CMOS process

A single chip quad-band multi-mode (GSM900/ DCS1800/PCS1900/CDMA2K) direct-conversion RF receiver with integrated baseband ADCs is presented. The fully integrated RF receiver is implemented in a 90-nm single poly, six level metal, standard digital CMOS process with no additional analog and RF components. The highly digital multi-mode receiver uses minimum analog filtering and AGC stages, digitizing useful signal, dynamic DC offsets and blockers at the mixer output. The direct-conversion GSM front-end utilizes resistive loaded LNAs with only two coupled inductors per LNA. The GSM front-end achieves a 31.5 dB gain and a 2.1 dB integrated noise figure with a 5 dB noise figure under blocking conditions. The CDMA2K front-end utilizes a self-biased common-gate input amplifier followed by passive mixers, achieving wideband input matching from 900 MHz up to 2.1 GHz with an IIP3 of +8 dBm. The GSM receiver consumes 38 mA from a power supply of 1.5 V and CDMA2K receiver consumes 16 mA in the low band and 21 mA in the high band. The multi-mode receiver, including LO buffers and frequency dividers, ADCs, and reference buffers, occupies 2.5 mm/sup 2/.

Chameleon: a dual-mode 802.11b/Bluetooth receiver system design

In this paper, an approach to map the Bluetooth and 802.11b standards specifications into an architecture and specifications for the building blocks of a dual-mode direct conversion receiver is proposed. The design procedure focuses on optimizing the performance in each operating mode while attaining an efficient dual-standard solution. The impact of the expected receiver nonidealities and the characteristics of each building block are evaluated through bit-error-rate simulations. The proposed receiver design is verified through a fully integrated implementation from low-noise amplifier to analog-to-digital converter using IBM 0.25-/spl mu/m BiCMOS technology. Experimental results from the integrated prototype meet the specifications from both standards and are in good agreement with the target sensitivity.

A 65nm CMOS DCXO system for generating 38.4MHz and a real time clock from a single crystal in 0.09mm 2

An integrated digitally-controlled crystal oscillator (DCXO) is presented that generates both 38.4 MHz and also a 32.768 kHz real time clock (RTC) from a single 38.4 MHz crystal. The DCXO can startup independently and transition seamlessly in and out of software control. The tuning range is 280 ppm with 2 ppb/step and guaranteed monotonicity. The phase noise is -135 dBc/Hz at 1kHz offset and -146 dBc/Hz at 10 kHz offset. The current consumption is 5 mA from a 1.4 V supply in full power mode and 234 μA in low power mode, including the LDO and all clock buffers. The DCXO is implemented in standard 65 nm digital CMOS with a die area of 0.09mm2.

A low-voltage charge pump for micro scale thermal energy harvesting

For energy harvesting applications, a power management unit (PMU) architecture operating at low input voltages is required. The most critical sub-blocks of such a PMU are the voltage multiplier and the low-voltage clock generator. An ultra-low-voltage exponential gain charge pump (ECP) that serves as a voltage multiplier for such PMUs is analyzed. A low-cost fully-integrated CMOS implementation for the ECP is proposed. Circuit simulations demonstrate a 0.85-0.90V output for input voltages as low as 150mV and static loads up to 1.5µA. The ECP was simulated in Cadence environment using a TSMC CMOS 65nm process and a total of 5nF MIM capacitors.

A low start up voltage charge pump for thermoelectric energy scavenging

In this paper, an ultra-low-voltage charge pump is presented. Two techniques are used to reduce required number of stages and improve power efficiency, namely clock boosting and Vt cancellation. Clock boosting is employed to increase the output voltage per stage resulting in lower number of stages, and hence smaller output resistance. Vt cancellation is achieved by using an auxiliary circuit that enables the charge pump to operate at input voltages as low as 300mV. Compared to conventional charge pump techniques, the proposed technique is shown to offer higher power efficiency and voltage gain. The charge pump is designed using TSMC 0.25µm CMOS technology.

A dual-mode low-pass filter for 802.11b/Bluetooth receiver

The design of a dual-mode low-pass channel selection filter for a dual-standard 802.11b/Bluetooth direct conversion receiver is presented. The filter is an OTA-C, 5/sup th/ order, Butterworth low pass structure. The OTA is implemented as a source-degenerated bipolar differential pair. Dual-mode operation, 600 kHz cut-off frequency for Bluetooth mode and 6 MHz for Wi-Fi mode, is achieved by switching the source-degeneration resistors and the capacitors. The filter operates from a single 2.5 V supply while consuming 2.7 mA and 0.9 mA for 802.11b and Bluetooth, respectively. It achieves 10 dBm in-band IIP3, 40 dBm out-of-band IIIP3 for both modes. The measured input referred noise density is -148.92 dBV/Hz and -140.48 dBV/Hz for 802.11b and Bluetooth, respectively.

A low-voltage CMOS bandgap reference circuit with improved power supply rejection

This paper presents a CMOS low-voltage bandgap reference circuit with improved power supply rejection (PSR). The analysis of the reference circuit shows the required condition to achieve high PSR. The proposed circuit incorporates a feedback loop to insure that the condition for high PSR is achieved across process variations and temperature drifts. The design has been implemented in 130nm CMOS process. It consumes 70µA from a single 1.2V supply. Simulation results show an improvement of more than 15dB in low frequency PSR due to the additional feedback loop. The theoretical and simulation results are in close agreement.

An integrated SAW-less narrowband RF front-end

In this paper an integrated SAW-less narrowband RF front-end for direct conversion wireless receivers is presented. The analysis of the feedback system shows a shift of the center frequency fRX for the overall RF bandpass filter from its nominal value fLO. The proposed architecture incorporates a notch filter at 2fLO to insure that there is no shift in fRX. The design has been implemented in 65nm CMOS process. It consumes 44mA from a single 1.2V supply. Simulation results show a rejection of more than 15dB in a bandwidth of +/−500MHz around 2GHz due to the additional feedback loop. The theoretical and simulation results are in close agreement.