Ahmed S. Mayet

Ga2O3 as both gate dielectric and surface passivation via sol-gel method at room ambient

We report the use of sol-gel method at room ambient to grow nanoscale thin film of Ga2O3 on Si surface for both surface passivation and gate dielectric. The admittance measurements were carried out in the frequency range of 20 kHz-1 MHz at room temperature. Voltage dependent profile of interfacial trap density (Dit) was obtained by using low and high frequency capacitance method. The capacitance (C)-voltage (V) analyses show that the structures have a low interfacial trap density (Dit) of 1x1012 cm-2eV-1. The Ga2O3 thin film synthesized via sol-gel method directly on devices to function as a gate dielectric film is found to be very effective. We also present our experimental results for a number of gate dielectric and device passivation applications.

Comparison of Heterojunction Device Parameters for Pure and Doped ZnO thin films with IIIA (Al or In) Elements Grown on Silicon at Room Ambient

In this work, pure and IIIA element doped ZnO thin films were grown on p type silicon (Si) with (100) orientated surface by sol-gel method, and were characterized for comparing their electrical characteristics. The heterojunction parameters were obtained from the current-voltage (I-V) and capacitance-voltage (C-V) characteristics at room temperature. The ideality factor (n), saturation current (Io) and junction resistance of ZnO/p-Si heterojunction for both pure and doped (with Al or In) cases were determined by using different methods at room ambient. Other electrical parameters such as Fermi energy level (EF), barrier height (ΦB), acceptor concentration (Na), built-in potential (Φi) and voltage dependence of surface states (Nss) profile were obtained from the C-V measurements. The results reveal that doping ZnO with IIIA (Al or In) elements to fabricate n-ZnO/p-Si heterojunction can result in high performance diode characteristics.

Optimization of light trapping micro-hole structure for high-speed high-efficiency silicon photodiodes

We optimized micro-holes in a thin slab for fast Si photodetectors at wavelength 800–950nm. Lateral modes are shown to be responsible for the effective light trapping. Small disorder and cone hole shapes helped achieve uniform quantum efficiency in a wide wavelength range.

Improved bandwidth and quantum efficiency in silicon photodiodes using photon-manipulating micro/nanostructures operating in the range of 700-1060 nm

Nanostructures allow broad spectrum and near-unity optical absorption and contributed to high performance low-cost Si photovoltaic devices. However, the efficiency is only a few percent higher than a conventional Si solar cell with thicker absorption layers. For high speed surface illuminated photodiodes, the thickness of the absorption layer is critical for short transit time and RC time. Recently a CMOS-compatible micro/nanohole silicon (Si) photodiode (PD) with more than 20 Gb/s data rate and with 52 % quantum efficiency (QE) at 850 nm was demonstrated. The achieved QE is over 400% higher than a similar Si PD with the same thickness but without absorption enhancement microstructure holes. The micro/nanoholes increases the QE by photon trapping, slow wave effects and generate a collective assemble of modes that radiate laterally, resulting in absorption enhancement and therefore increase in QE. Such Si PDs can be further designed to enhance the bandwidth (BW) of the PDs by reducing the device capacitance with etched holes in the pin junction. Here we present the BW and QE of Si PDs achievable with micro/nanoholes based on a combination of empirical evidence and device modeling. Higher than 50 Gb/s data rate with greater than 40% QE at 850 nm is conceivable in transceivers designed with such Si PDs that are integrated with photon trapping micro and nanostructures. By monolithic integration with CMOS/BiCMOS integrated circuits such as transimpedance amplifiers, equalizers, limiting amplifiers and other application specific integrated circuits (ASIC), the data rate can be increased to more than 50 Gb/s.

Highly efficient silicon solar cells designed with photon trapping micro/nano structures

Crystalline silicon (c-Si) remains the most commonly used material for photovoltaic (PV) cells in the current commercial solar cells market. However, current technology requires “thick” silicon due to the relative weak absorption of Si in the solar spectrum. We demonstrate several CMOS compatible fabrication techniques including dry etch, wet etch and their combination to create different photon trapping micro/nanostructures on very thin c-silicon surface for light harvesting of PVs. Both, the simulation and experimental results show that these photon trapping structures are responsible for the enhancement of the visible light absorption which leads to improved efficiency of the PVs. Different designs of micro/nanostructures via different fabrication techniques are correlated with the efficiencies of the PVs. Our method can also drastically reduce the thickness of the c-Si PVs, and has great potential to reduce the cost, and lead to highly efficient and flexible PVs.

Inhibiting device degradation induced by surface damages during top-down fabrication of semiconductor devices with micro/nano-scale pillars and holes

High-aspect ratio semiconductor pillar- and hole-based structures are being investigated for photovoltaics, energy harvesting devices, transistors, and sensors. The fabrication of pillars and holes frequently involves top-down fabrication (such as dry etching) of semiconductors. Such a process contributes to different types of crystalline defects including vacancies, interstitials, dislocations, stacking faults, surface roughness, impurities, and charging effects. These defects contribute to degraded device characteristics impacting detection sensitivity, energy conversion efficiency, etc. In this presentation, we review dry-etched semiconductor devices and demonstrate several possible methods to inhibit device degradation induced by surface damage. These methods include hydrogen passivation, the growth of oxide passivating thin films using wet furnace growth, and low-ion energy etching. These methods contributed to a leakage current reduction by as much as four orders of magnitude.

Efficient Si photovoltaic devices with integrated micro/nano holes

Efficient light harvesting in a thin layer of crystalline Si can be realized by implementing nanoscale pillars and holes to the device structure. The major drawback of the pillars and holes based photovoltaic devices is high surface to volume ratio, contributing to an increase in surface recombination rate of the photo-generated carriers. The common techniques used in pillars/holes fabrication such as dry etching make the surface even worse by bombarding it with high energy ions. Therefore, such damaged surfaces of high aspect ratio structures need to be effectively passivated. In this study, we demonstrate a hole based thin crystalline Si photovoltaic device with enhanced open circuit voltage and short circuit current after a successful surface passivation process through a wet oxidation. In addition, the effect of passivation layer fabricated by rapid thermal oxide growth on photo response is investigated. A successful fabrication of thin crystalline Si solar cells can lead to the applications of ultra-thin, highly efficient, flexible and wearable energy sources.