Toshishige Yamada

Metal?nanocarbon contacts

To realize nanocarbons in general and carbon nanotube (CNT) in particular as on-chip interconnect materials, the contact resistance stemming from the metal?CNT interface must be well understood and minimized. Understanding the complex mechanisms at the interface can lead to effective contact resistance reduction. In this study, we compile existing published results and understanding for two metal?CNT contact geometries, sidewall or side contact and end contact, and address key performance characteristics which lead to low contact resistance. Side contacts typically result in contact resistances >1 k?, whereas end contacts, such as that for as-grown vertically aligned CNTs on a metal underlayer, can be substantially lower. The lower contact resistance for the latter is due largely to strong bonding between edge carbon atoms with atoms on the metal surface, while carrier transport across a side-contacted interface via tunneling is generally associated with high contact resistance. Analyses of high-resolution images of interface nanostructures for various metal?CNT structures, along with their measured electrical characteristics, provide the necessary knowledge for continuous improvements of techniques to reduce contact resistance. Such contact engineering approach is described for both side and end-contacted structures.

Electron-beam and ion-beam-induced deposited tungsten contacts for carbon nanofiber interconnects

Ion-beam-induced deposition (IBID) and electron-beam-induced deposition (EBID) with tungsten (W) are evaluated for engineering electrical contacts with carbon nanofibers (CNFs). While a different tungsten-containing precursor gas is utilized for each technique, the resulting tungsten deposits result in significant contact resistance reduction. The performance of CNF devices with W contacts is examined and conduction across these contacts is analyzed. IBID-W, while yielding lower contact resistance than EBID-W, can be problematic in the presence of on-chip semiconducting devices, whereas EBID-W provides substantial contact resistance reduction that can be further improved by current stressing. Significant differences between IBID-W and EBID-W are observed at the electrode contact interfaces using high-resolution transmission electron microscopy. These differences are consistent with the observed electrical behaviors of their respective test devices.

Modeling of a carbon nanotube ultracapacitor

We report a study on modeling carbon nanotube (CNT) ultracapacitor performance, utilizing molecular dynamics to obtain solutions of Poissons equation within the capacitor cell. For a given voltage, the total current is computed based on the electric field generated from the nanotube electrodes and the friction caused by the motion of the electrolyte ions, yielding the frequency-dependent impedance. From the current and impedance behavior at a given frequency, we extract the Nyquist and Cyclic-Voltammetry plots for the simulated ultracapacitor. These plots compare well with existing experimental data. The behavior of the capacitor is further analyzed based on simulated spatial distributions of electrolyte ions.

Black holes enabled light bending and trapping in ultrafast silicon photodetectors

Micro and nanoscale holes on the surfaces of indirect band gap semiconductors such as silicon can enable perpendicular light bending and trapping of photons to enhance the light material interactions and absorption by orders of magnitude. The ‘bending’ of a vertically oriented light beam at nearly 90 degrees can be visualized as radial waves generated by a pebble dropped into a calm pool of water. Such bending and photon trapping result in an increased optical absorption path enabling very high light absorption coefficients. This observation led to the design of silicon photodetectors with high broadband efficiency above 50% and record ultrafast response contributing to more than 40 billion bits of data per second (Gb/s) communication speed.

Optimization of light trapping micro-hole structure for high-speed high-efficiency silicon photodiodes

We optimized micro-holes in a thin slab for fast Si photodetectors at wavelength 800–950nm. Lateral modes are shown to be responsible for the effective light trapping. Small disorder and cone hole shapes helped achieve uniform quantum efficiency in a wide wavelength range.

Improved bandwidth and quantum efficiency in silicon photodiodes using photon-manipulating micro/nanostructures operating in the range of 700-1060 nm

Nanostructures allow broad spectrum and near-unity optical absorption and contributed to high performance low-cost Si photovoltaic devices. However, the efficiency is only a few percent higher than a conventional Si solar cell with thicker absorption layers. For high speed surface illuminated photodiodes, the thickness of the absorption layer is critical for short transit time and RC time. Recently a CMOS-compatible micro/nanohole silicon (Si) photodiode (PD) with more than 20 Gb/s data rate and with 52 % quantum efficiency (QE) at 850 nm was demonstrated. The achieved QE is over 400% higher than a similar Si PD with the same thickness but without absorption enhancement microstructure holes. The micro/nanoholes increases the QE by photon trapping, slow wave effects and generate a collective assemble of modes that radiate laterally, resulting in absorption enhancement and therefore increase in QE. Such Si PDs can be further designed to enhance the bandwidth (BW) of the PDs by reducing the device capacitance with etched holes in the pin junction. Here we present the BW and QE of Si PDs achievable with micro/nanoholes based on a combination of empirical evidence and device modeling. Higher than 50 Gb/s data rate with greater than 40% QE at 850 nm is conceivable in transceivers designed with such Si PDs that are integrated with photon trapping micro and nanostructures. By monolithic integration with CMOS/BiCMOS integrated circuits such as transimpedance amplifiers, equalizers, limiting amplifiers and other application specific integrated circuits (ASIC), the data rate can be increased to more than 50 Gb/s.

Highly efficient silicon solar cells designed with photon trapping micro/nano structures

Crystalline silicon (c-Si) remains the most commonly used material for photovoltaic (PV) cells in the current commercial solar cells market. However, current technology requires “thick” silicon due to the relative weak absorption of Si in the solar spectrum. We demonstrate several CMOS compatible fabrication techniques including dry etch, wet etch and their combination to create different photon trapping micro/nanostructures on very thin c-silicon surface for light harvesting of PVs. Both, the simulation and experimental results show that these photon trapping structures are responsible for the enhancement of the visible light absorption which leads to improved efficiency of the PVs. Different designs of micro/nanostructures via different fabrication techniques are correlated with the efficiencies of the PVs. Our method can also drastically reduce the thickness of the c-Si PVs, and has great potential to reduce the cost, and lead to highly efficient and flexible PVs.

Inhibiting device degradation induced by surface damages during top-down fabrication of semiconductor devices with micro/nano-scale pillars and holes

High-aspect ratio semiconductor pillar- and hole-based structures are being investigated for photovoltaics, energy harvesting devices, transistors, and sensors. The fabrication of pillars and holes frequently involves top-down fabrication (such as dry etching) of semiconductors. Such a process contributes to different types of crystalline defects including vacancies, interstitials, dislocations, stacking faults, surface roughness, impurities, and charging effects. These defects contribute to degraded device characteristics impacting detection sensitivity, energy conversion efficiency, etc. In this presentation, we review dry-etched semiconductor devices and demonstrate several possible methods to inhibit device degradation induced by surface damage. These methods include hydrogen passivation, the growth of oxide passivating thin films using wet furnace growth, and low-ion energy etching. These methods contributed to a leakage current reduction by as much as four orders of magnitude.

Transport in fused InP nanowire device in dark and under illumination: Coulomb staircase scenario

Electron transport is discussed for an ensemble of fused conical indium phosphide nanowires bridging two hydrogenated n+-silicon electrodes. The current-voltage (Id-Vd) characteristics exhibit a Coulomb staircase in dark with a period of ~ 1 V but it disappears under light illumination in some devices, while Id-Vd is featureless smooth monotonic curve in other devices. It is shown that transport is dominated by a single NW pair in dark, while many NW pairs will contribute to transport under illumination.sentati

Coulomb staircase in fused semiconducting InP nanowires under light illumination

Detailed electron transport analysis is performed for an ensemble of conical indium phosphide nanowires bridging two hydrogenated n+-silicon electrodes. The current-voltage (Id-Vd) characteristics exhibit a Coulomb staircase in dark with a period of ~ 1 V at room temperature. The staircase is found to disappear under light illumination. This observation can be explained by assuming the presence of a tiny Coulomb island, and its existence is possible due to the large surface depletion region created within contributing nanowires. Electrons tunnel in and out of the Coulomb island, resulting in the Coulomb staircase Id-Vd. Applying light illumination raises the electron quasi-Fermi level and the tunneling barriers are buried, causing the Coulomb staircase to disappear.