Aida Todri-Sanial

Computing detection probability of delay defects in signal line tsvs

Three-dimensional stacking technology promises to solve the interconnect bottleneck problem by using Through-Silicon-Vias (TSVs) to vertically connect circuit layers. However, manufacturing steps may lead to partly broken or incompletely filled TSVs that may degrade the performance and reduce the useful lifetime of a 3D IC. Due to combinations of physical factors such as switching activity, supply noise and crosstalk, path delays can experience speed-up or slow-down that could let the effect of resistive open TSV go undetected by conventional test methods. In this work, we present a metric based on probabilistic analysis to detect delay defects induced by resistive opens that occur on signal line TSVs. Our experimental result will show the accuracy of the proposed metric.

A Survey of Carbon Nanotube Interconnects for Energy Efficient Integrated Circuits

This article is a review of the state-of-art carbon nanotube interconnects for Silicon application with respect to the recent literature. Amongst all the research on carbon nanotube interconnects, those discussed here cover 1) challenges with current copper interconnects, 2) process & growth of carbon nanotube interconnects compatible with back-end-of-line integration, and 3) modeling and simulation for circuit-level benchmarking and performance prediction. The focus is on the evolution of carbon nanotube interconnects from the process, theoretical modeling, and experimental characterization to on-chip interconnect applications. We provide an overview of the current advancements on carbon nanotube interconnects and also regarding the prospects for designing energy efficient integrated circuits. Each selected category is presented in an accessible manner aiming to serve as a survey and informative cornerstone on carbon nanotube interconnects relevant to students and scientists belonging to a range of fields from physics, processing to circuit design.

A novel method to mitigate TSV electromigration for 3D ICs

Three-dimensional (3D) integration is considered to be a promising technology to tackle the global interconnect scaling problem for tera-scale integrated circuits (ICs). 3D ICs typically employ through-silicon-vias (TSVs) to connect planar circuits vertically. Due to its immature fabrication process, several defects such as void, misalignment and dust contamination, may be introduced. These defects can increase current densities within TSVs significantly and cause severe electromigration (EM) effect, which can degrade the reliability of 3D ICs considerably. In this paper, we propose a novel method to mitigate EM effect of the defective TSV. At first, we analyze various possible TSV defects and demonstrate that they can aggravate electromigration dramatically. Based on the observation that EM effect can be alleviated significantly by balancing the direction of current flow within TSV, we design an on-line self-healing circuit to protect defective TSVs, which can be detected during test procedure, from EM without degrading performance. Experimental results show that our proposed method can achieve tens times improvement on mean time to failure (MTTF) compared to the design without using such method with negligible hardware overheads and power consumption.

Electrothermal Analysis of Carbon Nanotubes Power Delivery Networks for Nanoscale Integrated Circuits

This paper presents a circuit-based self-consistent electrothermal model of Power Delivery Networks (PDNs) fabricated with carbon nanotubes, for nanoscale integrated circuits. It couples the electrical submodel with an equivalent circuit submodel of the thermal problem, and allows characterizing the PDNs in terms of both voltage drop and temperature rise. The temperature dependence of the PDNs electrical parameters is taken into account through physically meaningful models of the mean free path and the number of conducting channels in carbon nanotubes. The model is used to compare the performance of conventional copper PDNs with those of PDNs realized with bundles of carbon nanotubes in different configurations (single-wall, multiwall, and mixed). The adopted values of thermal and electrical parameters are those typically obtainable with the current fabrication processes, for technology nodes of 65 and 22 nm and different core power consumption.

Performance exploration of partially connected 3D NoCs under manufacturing variability

Several Through-Silicon-Vias (TSVs) may present resistive and open defects due to 3D manufacture variability. This paper advocates the use of 3D Network-on-Chip (NoC) with asynchronous communication interfaces to cope with significant variations in TSV propagation delays. The technique uses serial communication in the vertical channels to reduce the number of TSVs. Based on a representative delay distribution, we compare the average performance considering a non-defective 3D NoC, one with resistive defective TSVs and one with resistive and open defective TSVs. Results show that it is better to adapt the interfaces to cope with large margins of delay than to avoid TSVs by using adaptive routing.

A Complete Resistive-Open Defect Analysis for Thermally Assisted Switching MRAMs

Magnetic random access memory (MRAM) is an emerging technology with potential to become the universal on-chip memory. Among existing MRAM technologies, thermally assisted switching (TAS)-MRAM technology offers several advantages compared with other technologies: selectivity, single magnetic field, and high-integration density. In this paper, we analyze the impact of resistive-open defects on TAS-MRAM behavior. Electrical simulations were performed on a hypothetical 16 word TAS-MRAM architecture enabling any combination of read and write operations. Results show that read and write sequences may be affected by resistive-open defects that may induce single and double-cell faulty behaviors. As a next step, we will exploit the analyses results to guide the test phase by providing effective test algorithms targeting faults related to actual defects affecting TAS-MRAM architectures.

An architecture-level cache simulation framework supporting advanced PMA STT-MRAM

With integration density on-chip rocketing up, leakage power dominates the whole power budget of contemporary CMOS technology based memory, especially for SRAM based on-chip cache. To overcome the aggravating “power wall” issue, some emerging memory technologies such as STT-MRAM (Spin transfer torque magnetic RAM), PCRAM (Phase change RAM), and ReRAM(Resistive RAM) are proposed as promising candidates for next generation cache design. Although there are several existing simulation tools available for cache design, such as NVSim and CACTI, they either cannot support the most advanced PMA (Perpendicular magnetic anisotropy) STT-MRAM model or lack the ability for multi-banked large capacity cache simulation. In this paper, we propose an architecture level design framework for cache design from device level up to array structure level, which can support the most advanced PMA STT-MRAM technology. The simulation results are analyzed and compared with those produced by NVSim, which prove the correctness of our framework. The potential benefits of PMA STT-MRAM used as multi-banked L2 and L3 cache are also investigated in the paper. We believe that our framework will be helpful for computer architecture researchers to adopt the PMA STT-MRAM in on-chip cache design.

TSV aware timing analysis and diagnosis in paths with multiple TSVs

3D-IC test becomes a challenge with the increasing number of TSVs and demands for effective 3D aware test techniques. In this work, we propose a timing aware model to capture delay variations on a path due to resistive open TSVs. The key idea is to analytically model delay and apply our correlation-based resistive open TSV detection method to attain path delay fault coverage. We propose two methods to investigate timing variation introduced by resistive open TSVs in a critical path delay with multiple TSVs. Method I computes the correlation of multiple TSVs in a path to overall path delay to determine if TSVs are the source of the introduced delay. Method II pinpoints which TSV is faulty by computing the delay fault coverage of each TSV in a path with multiple TSVs. Our results indicate the accuracy of our proposed method and promotes early identification of resistive open defects TSVs.

Exploring potentials of perpendicular magnetic anisotropy STT-MRAM for cache design

Traditional CMOS integrated circuits suffer from elevated power consumption as technology node advances. A few emerging technologies are proposed to deal with this issue. Among them, STT-MRAM is one of the most important candidates for future on-chip cache design. However, most STT-MRAM based architecture level evaluations focus on in-plane magnetic anisotropy effect. In the paper, we evaluate the most advanced perpendicular magnetic anisotropy (PMA) STT-MRAM for on-chip cache design in terms of performance, area and power consumption perspectively. The experimental results show that PMA STT-MRAM has higher power efficiency compared to SRAM as well as desirable scalability with technology node shrinking.

Power supply noise-aware workload assignments for homogeneous 3D MPSoCs with thermal consideration

In order to improve performance and reduce cost, multi-processor system on chip (MPSoC) is increasingly becoming attractive. At the same time, 3D integration emerges as a promising technology for high density integration. 3D homogeneous MPSoCs combine the benefits of both. However, high current demand and large on-chip switching activity variations introduce severe power supply noises (PSN) for 3D MPSoCs, which can increase critical path delay, and degrade chip performance and reliability. Meanwhile, thermal gradient should also be considered for 3D MPSoCs to avoid hot spots. In the paper, we investigate the PSN effects of different workloads and propose an effective PSN estimation method. Then, a heuristic workload assignment algorithm is proposed to suppress PSN under the given thermal constraint. The experimental results show that PSNs can be reduced significantly compared with thermal-balanced workload assignment scheme, and the system performance can be improved as well.