Weisheng Zhao

High Speed, High Stability and Low Power Sensing Amplifier for MTJ/CMOS Hybrid Logic Circuits

Densely embedding Magnetic Tunnel Junctions (MTJ) in CMOS logic circuits is considered as one potentially powerful solution to bring non volatility, instant on/off and low standby power in todays programmable logic circuits, in order to overcome major drawbacks while preserving high operation speed. A critical issue in this process is the integration of MTJ electric signal to CMOS electronics, in particular the requirement of ldquozerordquo read/write error for logic applications. In this paper, we propose a new sense amplifier circuit, called Pre-Charge Sense Amplifier (PCSA). This circuit, comprising 7 CMOS transistors at minimum size, is able to read the magnetic configuration of a pair of magnetic tunnel junctions with opposite configurations at high speed (about 200 ps), with very low power and error rate compared to previously proposed solutions. Simulations using a ST Microelectronics 90 nm design kit and a compact model of MTJ demonstrate the performances of PCSA.

Compact Modeling of Perpendicular-Anisotropy CoFeB/MgO Magnetic Tunnel Junctions

Magnetic tunnel junctions (MTJs) composed of ferromagnetic layers with perpendicular magnetic anisotropy (PMA) are of great interest for achieving high-density nonvolatile memory and logic chips owing to its scalability potential together with high thermal stability. Recent progress has demonstrated a capacity for high-speed performance and low power consumption through current-induced magnetization switching. In this paper, we present a compact model of the CoFeB/MgO PMA MTJ, a system exhibiting the best tunnel magnetoresistance ratio and switching performance. It integrates the physical models of static, dynamic, and stochastic behaviors; many experimental parameters are directly included to improve the agreement of simulation with experimental measurements. Mixed simulation based on the 65-nm technology node of a magnetic flip-flop validates its relevance and efficiency for MTJ/CMOS memory and logic chip design.

Strain-controlled magnetic domain wall propagation in hybrid piezoelectric/ferromagnetic structures

The control of magnetic order in nanoscale devices underpins many proposals for integrating spintronics concepts into conventional electronics. A key challenge lies in finding an energy-efficient means of control, as power dissipation remains an important factor limiting future miniaturization of integrated circuits. One promising approach involves magnetoelectric coupling in magnetostrictive/piezoelectric systems, where induced strains can bear directly on the magnetic anisotropy. While such processes have been demonstrated in several multiferroic heterostructures, the incorporation of such complex materials into practical geometries has been lacking. Here we demonstrate the possibility of generating sizeable anisotropy changes, through induced strains driven by applied electric fields, in hybrid piezoelectric/spin-valve nanowires. By combining magneto-optical Kerr effect and magnetoresistance measurements, we show that domain wall propagation fields can be doubled under locally applied strains. These results highlight the prospect of constructing low-power domain wall gates for magnetic logic devices.

Spin transfer torque (STT)-MRAM--based runtime reconfiguration FPGA circuit

As the minimum fabrication technology of CMOS transistor shrink down to 90nm or below, the high standby power has become one of the major critical issues for the SRAM-based FPGA circuit due to the increasing leakage currents in the configuration memory. The integration of MRAM in FPGA instead of SRAM is one of the most promising solutions to overcome this issue, because its nonvolatility and high write/read speed allow to power down completely the logic blocks in “idle” states in the FPGA circuit. MRAM-based FPGA promises as well as some advanced reconfiguration methods such as runtime reconfiguration and multicontext configuration. However, the conventional MRAM technology based on field-induced magnetic switching (FIMS) writing approach consumes very high power, large circuit surface and produces high disturbance between memory cells. These drawbacks prevent FIMS-MRAMs further development in memory and logic circuit. Spin transfer torque (STT)-based MRAM is then evaluated to address these issues, some design techniques and novel computing architecture for FPGA logic circuits based on STT-MRAM technology are presented in this article. By using STMicroelectronics CMOS 90nm technology and a STT-MTJ spice model, some chip characteristic results as the programming latency and power have been calculated and simulated to demonstrate the expected performance of STT-MRAM based FPGA logic circuits.

Macro-model of Spin-Transfer Torque based Magnetic Tunnel Junction device for hybrid Magnetic-CMOS design

The development of hybrid magnetic-CMOS circuits such as MRAM (magnetic RAM) and magnetic logic circuit requires efficient simulation models for the magnetic devices. A macro-model of magnetic tunnel junction (MTJ) is presented in this paper. This device is the most commonly used magnetic components in CMOS circuits. This model is based on spin-transfer torque (STT) writing approach. This very promising approach should constitute the second generation of MRAM switching technology; it features small switching current (~120uA) and high programming speed (<1ns). The macro-model has been developed in Verilog-A language and implemented on Cadence Virtuoso platform with Spectre 5.0.32 simulator. Many experimental parameters are integrated in this model to improve the simulation accuracy. So, the model can efficiently be used to design hybrid magnetic CMOS circuits

Perpendicular-magnetic-anisotropy CoFeB racetrack memory

Current-induced domain wall motion in magnetic nanowires drives the invention of a novel ultra-dense non-volatile storage device, called “racetrack memory.” Combining with magnetic tunnel junctions write and read heads, CMOS integrability and fast data access speed can also be achieved. Recent experimental progress showed that perpendicular-magnetic anisotropy (PMA) CoFeB could be a good candidate to build up racetrack memory and promise high performance like high-density (e.g., ∼1 F2/bit), fast-speed, and low-power beyond classical spin transfer torque memories. In this paper, we first present the design of PMA CoFeB racetrack memory and a spice-compatible model to perform mixed simulation with CMOS circuits. Its area, speed, and power dissipation performance has been simulated and evaluated based on different technology nodes.

Robust neural logic block (NLB) based on memristor crossbar array

Neural networks are considered as promising candidates for implementing functions in memristor crossbar array with high tolerance to device defects and variations. Based on such arrays, Neural Logic Blocks (NLB) with learning capability can be built to replace Configurable Logic Block (CLB) in programmable logic circuits. In this article, we describe a neural learning method to implement Boolean functions in memristor NLB. By using Monte-Carlo simulation, we demonstrate its high robustness against most important device defects and variations, like static defects and memristor voltage threshold variability.

Spin-MTJ based Non-volatile Flip-Flop

Spin Transfer Torque (STT) writing approach based Magnetic Tunnel Junction (Spin-MTJ) is the excellent candidate to be used as Spintronics device in Magnetic RAM (MRAM) and Magnetic Logic. We present the first Non-volatile Flip-Flop based on this device for Field Programmable Gate Array (FPGA) and System On Chip (SOC) circuits, which can make these circuits fully non-volatile by storing permanently all the data processed in the Spin-MTJ memory cells. The non-volatility enables logic circuits to decrease significantly the start-up latency of these circuits from some micro seconds down to some hundred pico seconds. By using St microelectronics 90 nm CMOS technology and a behavior Spin-MTJ simulation Model in Verilog-A language, this non-volatile Flip-Flop has been demonstrated that it works not only in very high speed or low propagation delay, but also keeps low power dissipation and small cell surface.

Two‐Terminal Carbon Nanotube Programmable Devices for Adaptive Architectures

2010 WILEY-VCH Verlag Gm Devices based on nanoscale objects with well-defined structures and original electronic properties are of great interest for the development of innovative electronic circuits, in particular if they offer novel functionalities (such as memory or sensing) and are compatible with large-scale self-assembly techniques. Among these devices, two-terminal ones such as memristors are attracting intense interest due to their potential superior capabilities in terms of integration. However, at the nanometer scale, one faces the critical issue of variability among devices, both in terms of device-to-device performances and in terms of precise positioning of individual objects. It is, thus, very unlikely that conventional circuit architectures developed for silicon complementary metal oxide semiconductor (CMOS) devices will be ideally suited for these new devices. Adaptive architectures comprising a programming or a learning step are probably more reasonable candidates, as they are naturally tolerant to variability. Targeting adaptive circuits is a challenging approach, which requires the development of devices that combine several key properties among which a well-controlled memory effect is the most critical. In this context, single-walled carbon nanotubes (SWNTs) are of special relevance, as they combine nanometer-scale size and 1D character with exceptional electronic, mechanical, and chemical properties. In particular, carbon nanotube-based field-effect transistors (CNTFETs), when aggressively scaled, compete favorably with predictions of ultimate silicon-based devices of the same size. However, circuits based on such three-terminal devices do not present sufficient improvement in terms of scaling, performances, and functionality to compensate for the strong issues related to their integration. Indeed, despite important progress in the field, there is still no satisfactory solution for the implementation of a pure CNTFET-based technology that would be useful in terms of function and competitive and compatible with existing technologies to allow their co-integration. Recently, we showed that CNTFETs, coated with a thin film of photoconductive polymer, combine light sensitivity with a strong and well-controlled non-volatile memory effect. In this Communication, we show that such optically gated carbon nanotube transistors (OG-CNTFETs) can be used as two-terminal memory devices, i.e., programmable resistors, which have all the required characteristics to serve as building blocks for adaptive architectures. In particular, the nanotube channel resistivity can be precisely adjusted in a very large range, spanning several orders of magnitudes (without using the gate electrode), and then stored in a non-volatile way. We also establish the capability to handle the programming of multiple devices and demonstrate how this approach addresses the crucial issue of variability among devices. All together, it shows that such mixed nanotube–polymer devices have all the characteristics of artificial synapses that can provide an elegant solution to build neural network types of circuits. The conductivity of an OG-CNTFETat a fixed source/drain bias (VDS) can be controlled independently using either a gate potential (VGS) or illumination at a wavelength corresponding to an absorption peak of the polymer. Such transistor can be built from an individual SWNT, as in our previous study, or from networks of SWNTs. Constructing circuits based on single-nanotube devices presents severe fabrication difficulties in the present state of development of the field, in particular, due to the mixing of metallic and semiconducting nanotubes in available sources and to the need for complex steps to achieve the precise positioning of individual nano-objects. Conversely, the use of dense networks of randomly oriented SWNTs allows the efficient fabrication of multiple and interconnected devices. Moreover, the use of parallel stripes of SWNTs as illustrated in Figure 1a and 2a allows obtaining routinely on/off (ION/IOFF) current ratios of several decades. [8] As we showed in ref. [9], such use of nanotube networks has no impact on the optical-gating mechanism so that the conclusions of the present work can be extended to the single-nanotube-device case. The transistors are fabricated as described in the Experimental section. In the dark, the devices behave as p-type Schottky transistors. Under illumination, the conductivity of the device increases due to the accumulation and trapping of photogenerated electrons at the nanotube/dielectric interface.

Spin-Transfer Torque Magnetic Memory as a Stochastic Memristive Synapse for Neuromorphic Systems

Spin-transfer torque magnetic memory (STT-MRAM) is currently under intense academic and industrial development, since it features non-volatility, high write and read speed and high endurance. In this work, we show that when used in a non-conventional regime, it can additionally act as a stochastic memristive device, appropriate to implement a “synaptic” function. We introduce basic concepts relating to spin-transfer torque magnetic tunnel junction (STT-MTJ, the STT-MRAM cell) behavior and its possible use to implement learning-capable synapses. Three programming regimes (low, intermediate and high current) are identified and compared. System-level simulations on a task of vehicle counting highlight the potential of the technology for learning systems. Monte Carlo simulations show its robustness to device variations. The simulations also allow comparing system operation when the different programming regimes of STT-MTJs are used. In comparison to the high and low current regimes, the intermediate current regime allows minimization of energy consumption, while retaining a high robustness to device variations. These results open the way for unexplored applications of STT-MTJs in robust, low power, cognitive-type systems.