Ajoy Kumar Palit

Crosstalk fault modeling in defective pair of interconnects

The manufacturing defect in the interconnect lines can lead to various electrical faults, e.g. defect due to under-etching effect/conductive particle contamination on interconnect line can lead to increased coupling capacitances between the two adjacent interconnects, which, in turn, can eventually result in crosstalk fault in the deep sub-micron (DSM) chips. In this paper, we describe the line-defect-based crosstalk fault model that will be helpful in analyzing the severity of the defect/fault, as the crosstalk fault occasionally leads to various signal integrity losses, such as timing violation due to excessive signal delay or speed-up, logic failure due to crosstalk positive/negative glitch above/below logic low/high threshold and also reliability problem particularly due to crosstalk glitch above logic high threshold. Our crosstalk fault model is very fast (at least 11 times faster than PSPICE model) and its accuracy is very close to PSPICE simulation results when the defect/fault is located in the middle of interconnects, whereas for the defects located at the near-end/far-end side of aggressor-victim the model accuracy differs marginally.

Backpropagation based training algorithm for Takagi-Sugeno type MIMO neuro-fuzzy network to forecast electrical load time series

Describes a backpropagation based algorithm that can be used to train the Takagi-Sugeno (TS) type multi-input multi-output (MIMO) neuro-fuzzy network efficiently. The training algorithm is efficient in the sense that it can bring the performance index of the network, such as the sum squared error (SSE), down to the desired error goal much faster than that the simple backpropagation algorithm (BPA). Finally, the above training algorithm is tested on neuro-fuzzy modeling and forecasting application of electrical load time series.

Nonlinear combination of forecasts using artificial neural network, fuzzy logic and neuro-fuzzy approaches

In the actual practice, it becomes interesting from the efficiency point of view to combine various forecasts of a specific time series into a single forecast and to interrogate the resulting forecasting accuracy. The combination is usually nonlinear. Various intelligent combination techniques have been suggested for this purpose, based on different neural network architectures, including the feedforward neural network and evolutionary neural network. In this paper, the nonlinear combination of time series forecasts is proposed, based on isolated use of neural networks, fuzzy logic and neuro-fuzzy systems. On some practical examples it is demonstrated that the nonlinear combination of a group of forecasts based on intelligent approach is capable of producing a single better forecast than any individual forecasts involved in the combination.

ABCD modeling of crosstalk coupling noise to analyze the signal integrity losses on the victim interconnect in DSM chips

The paper proposes an ABCD modeling approach to model the crosstalk coupling noise on the victim interconnect due to single/multiple aggressor(s) in deep sub-micron (DSM) chips. After the order reduction the crosstalk model is utilized for the analysis of crosstalk coupling noise on the victims far end signal. Various timing issues related to signal waveform such as, delay time, overshoot and undershoot occurrence time etc., that in effect help to ensure in prior the desired signal integrity (SI) and performance reliability of the SoCs, can be estimated analytically using the reduced order crosstalk model. It has been observed that the crosstalk coupling noise introduces the delay in the victims far end signal which can be significant enough or even unacceptable if many aggressors simultaneously couple energy to the victim line, or the line spacing between the aggressor and victim is reduced due to manufacturing defect such as under-etching or even, length of the victim interconnect is increased due to improper layouts of / routings between cores and devices on chips. Influences of other interconnect parasitics on the victims far end signal can also be analyzed using the same model. Simulation results obtained with the proposed reduced order model is found to be quite comparable to the accuracy of the PSPICE simulation.

Modeling and analysis of crosstalk coupling effect on the victim interconnect using the ABCD network model

After order reduction, the crosstalk model is utilized for the analysis of crosstalk coupling effects on the victims output signal. Various timing issues related to signal waveform such as, delay time, overshoot and undershoot occurrence time etc., that in effect help to ensure the desired signal integrity (SI) and performance reliability of the SoCs, can be estimated analytically using the reduced order crosstalk model. It has been observed that the crosstalk coupling effect introduces a delay in the victims output signal which can be significant enough, or even unacceptable, if many aggressors simultaneously couple energy to the victim line, or the line spacing between the aggressor and victim is reduced due to under-etching ,or even, the length of the victim interconnect is increased because of improper layout/routing. Influences of other interconnect parasitics on the victims output signal can also be tested using the same model. Simulation results obtained with our reduced order model is found to be quite good and comparable to the accuracy of PSPICE simulation.

Forecasting chaotic time series using neuro-fuzzy approach

A neuro-fuzzy approach for forecasting of chaotic time series is proposed, based on neuro-implementation of a fuzzy logic system with the Gaussian membership functions. To construct the neuro-fuzzy system that will approximate and forecast the future values of a chaotic time series, the parameters of the membership functions, i.e. the mean (c) and the variance (/spl sigma/) of the selected Gaussian functions, as well as the center of fuzzy region (y/sup l/) are to be adjusted either by backpropagation or the Levenberg-Marquardt training algorithm. To examine the effectiveness of the forecasting method the performance function, like the sum squared errors, mean squared errors, and mean absolute errors, are evaluated. In this way it was shown that the proposed neuro-fuzzy approach is an excellent tool for chaotic time series prediction.

Equivalent victim model of the coupled interconnects for simulating crosstalk induced glitches and delays

Noise effects due to parasitic couplings between two closely located neighboring wires have significant impact on the performance of the DSM chips. Analysis of a single wire with all its couplings is required to find out the maximum effect of the crosstalk noise both in terms of glitch and delay. This paper introduces a decoupled RLGC transient model for victim wire which is highly accurate and flexible. This model can be used to compute the maximum delay and glitch effect due to crosstalk on a victim wire under different slew rates and delays of aggressor and victim signals. The equivalent victim models accuracy is validated by the PSPICE simulation results and yet the simulation speed is at least 13 times faster than the latter.

Fuzzy logic based automatic rule generation and forecasting of time series

An algorithm is proposed that automatically generates the fuzzy rules from time series data and can subsequently be used for forecasting of the same time series. The effectiveness of the algorithm, measured by the performance indices such as the sum squared error (SSE), root mean squared error (RMSE/MSE) and the mean absolute error (MAE), is demonstrated on forecasting of chaotic time series, as well as on forecasting of homogeneous non-stationary time series with and without seasonality and trend components.

Test Pattern Generation and Compaction for Crosstalk Induced Glitches and Delay Faults

VLSI circuits have become more susceptible to signal integrity related failures with the ever decreasing process geometries. Detection of crosstalk induced faults is thus important as capacitive crosstalk is one of the major sources of signal integrity related failures. Crosstalk glitch can result in erroneous output if the glitch effect propagates to a primary output or to an intermediate flip-flop. Similarly the crosstalk induced delay effects can also result in latching of an incorrect value if the delay exceeds the allowed margins. In this work a test generation and compaction method is proposed for crosstalk faults. Test patterns are generated by simultaneously considering the coupling capacitance, timing and functional incompatibilities between the victim and aggressor nets, to produce the practical maximum crosstalk noise. A unique method is proposed for finding the functional incompatibilities between interconnects. The generated test set is then compacted initially through pattern merging and then further through the fault-chaining algorithm. Three different implementations of this algorithm are compared on crosstalk test sets generated for ISCAS’85 benchmark circuits. Results show considerable reduction in crosstalk pessimism for the given layout and timing, as well as up to 75% reduction in overall test set size.

A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips

In this paper a new, flexible and a very accurate crosstalk fault model is developed which considers the capacitive coupling noise between the aggressor and the victim interconnect in deep sub-micron chips. The proposed crosstalk model is based on the distributed ABCD model of a long on-chip interconnect and takes into account the CMOS driver and receiver parameters of both aggressor and victim interconnects, besides the consideration of usual distributed per-unit-length RLGC parasitic elements and coupling capacitance, and interconnect’s length. Simulations are all carried out using the Philips CMOS12 (130nm) technology parameters and the model accuracy is found very much close to PSPICE simulation result. The same model can further be utilized to analyze/estimate the influence of interconnect parasitics on various signal integrity losses such as delay, glitch, overshoot, or crosstalk hazards (if any).