Kishore K. Duganapalli

Crosstalk fault modeling in defective pair of interconnects

The manufacturing defect in the interconnect lines can lead to various electrical faults, e.g. defect due to under-etching effect/conductive particle contamination on interconnect line can lead to increased coupling capacitances between the two adjacent interconnects, which, in turn, can eventually result in crosstalk fault in the deep sub-micron (DSM) chips. In this paper, we describe the line-defect-based crosstalk fault model that will be helpful in analyzing the severity of the defect/fault, as the crosstalk fault occasionally leads to various signal integrity losses, such as timing violation due to excessive signal delay or speed-up, logic failure due to crosstalk positive/negative glitch above/below logic low/high threshold and also reliability problem particularly due to crosstalk glitch above logic high threshold. Our crosstalk fault model is very fast (at least 11 times faster than PSPICE model) and its accuracy is very close to PSPICE simulation results when the defect/fault is located in the middle of interconnects, whereas for the defects located at the near-end/far-end side of aggressor-victim the model accuracy differs marginally.

A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips

In this paper a new, flexible and a very accurate crosstalk fault model is developed which considers the capacitive coupling noise between the aggressor and the victim interconnect in deep sub-micron chips. The proposed crosstalk model is based on the distributed ABCD model of a long on-chip interconnect and takes into account the CMOS driver and receiver parameters of both aggressor and victim interconnects, besides the consideration of usual distributed per-unit-length RLGC parasitic elements and coupling capacitance, and interconnect’s length. Simulations are all carried out using the Philips CMOS12 (130nm) technology parameters and the model accuracy is found very much close to PSPICE simulation result. The same model can further be utilized to analyze/estimate the influence of interconnect parasitics on various signal integrity losses such as delay, glitch, overshoot, or crosstalk hazards (if any).

Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects

The paper addresses here the fault model of particular type of manufacturing defects in the metal layers of deep sub-micron (DSM) chips, e.g. conductive particle contamination, bad handling or under-etching defects in the pair of parallel interconnects which lead to both severe non-zero resistive bridging fault and increased crosstalk coupling fault between the on-chip aggressor-victim interconnects. The developed fault model is very helpful in analyzing the severity of defect and can also be utilized for determination of its critical value, below which device will continue to behave as defect tolerant, however, exceeding the critical value the defect may manifest other complex functionality and reliability problems of the device. Experimental simulations carried out with Philips CMOS12 (130 nm) technology parameters reveal twofold electrical effect of the defect. For instance, non-zero resistive bridging fault has major effect on the final steady-state value of the victims output signal waveform, whereas the crosstalk coupling fault has major effect on the delay as well as crosstalk glitch height of the victims output waveform. It has been further observed that the defects severity is highly dependent on defects location because the same defect is less severe (measured in terms of victims delay and crosstalk glitch height) when the defect is located at the near end side of interconnects, whereas it becomes more and more severe when the same defect is located in the middle and far end side of interconnects

Distributed RLGC transient model of coupled interconnects in DSM chips for crosstalk noise simulation

Noise effects in coupled interconnects, i.e. crosstalk induced glitch and crosstalk induced delay can significantly impact the performance of deep sub-micron (DSM) chips. Therefore, in this paper distributed RLGC transient model of coupled interconnects has been developed that will be useful for analyzing such crosstalk noise effects in DSM chips. The model accuracy is quite comparable to the PSPICE simulation results and yet the simulation speed is at least 11 times faster than the latter.

Test pattern generation for worst-case crosstalk faults in DSM chips using Genetic Algorithm

Nowadays, aggressive scaling of transistor dimensions has led to the reduction of process geometries and thereby higher device density in DSM chips. Higher signal switching speeds and increased aspect ratios of interconnects in chips has enforced the attention towards non conventional faults due to the coupling noise between adjacent interconnects. Crosstalk is one such major Signal Integrity issue, that can occur intermittently or permanently, which may lead to functional problems and even occasionally for failure of the chip. Testing the chips for such faults is essential even after manufacturing with certain design constraints to ensure the quality of the chip. Predetermined test patterns are necessary for testing such crosstalk related faults. In this paper, an elitist genetic algorithm has been developed to determine the test patterns for worst-case crosstalk faults. Fitness functions for all basic gates also based on the level of the gates have been developed. The algorithm was performed on some benchmark circuits and the determined test patterns were also verified.

Genetic-Algorithm-based Test Pattern Generation for Crosstalk Faults between On-Chip Aggressor and Victim

With the shrinking feature size and increasing aspect ratios of interconnects in DSM chips, the coupling noise between adjacent interconnects has become a major signal integrity (SI) issue, giving rise to crosstalk failures. In older technologies, SI issues have been ignored because of high noise immunity of the CMOS circuits and the process technology. However, as CMOS technologies lower down the supply voltage as well as the threshold voltage of a transistor, digital designs are more and more susceptible to noise because of the reduction of noise margin. The genetic algorithms (GAs) have been applied earlier in different engineering disciplines as potentially good optimization tools and for various applications in VLSI design, layout, EDIF digital system testing and also for test automation, particularly for stuck-at-faults and crosstalk-induced delay faults. In this paper, an elitist GA has been developed that can be used as an ATPG tool for generating the test patterns for crosstalk-induced faults between on-chip aggressor and victim and as well as for stuck-at-faults. It has been observed that the elitist GA, when the fitness function is properly defined, has immense potential in extracting the suitable test vectors quickly from randomly generated initial patterns.

TPG for Crosstalk Faults between On-Chip Aggressor and Victim Using Genetic Algorithms

The coupling noise between adjacent interconnects has become major SI issue, due to higher aspect ratios of interconnects in DSM chips, giving rise to crosstalk failures. The Genetic Algorithms (GA) have been applied earlier in different engineering disciplines as potentially good optimization tools and also for various applications in VLSI Design, layout, EDIF digital system testing and also for test automation, particularly for stuck-at-faults and crosstalk-induced delay faults. In this paper, an elitist GA has been developed that can be used as an ATPG tool for generating the test patterns for crosstalk-induced faults between on-chip aggressor and victim and as well as for stuck-at faults. It has been observed that the elitist GA, when the fitness function is properly defined, has immense potential in extracting the suitable test vectors quickly from randomly generated initial patterns.

Determination of Critical Parameters for Crosstalk Faults between On-chip Interconnects using Worst-Case Methods

Interconnects being the limiting factor for both performance and density in todays VLSI systems, interconnect parasitics are considered to be the prime sources of signal integrity problems. Line inductance and/or mutual inductance in certain interconnect lines usually give rise to overshoots and undershoots in voltage waveforms which may cause reliability concerns in circuits, cause glitches and may lead to false transitions at the gate output. Therefore, it is important to track down the limiting values or the critical parameters of influential parameters below which a fault tolerant behavior of the device can be guaranteed. Earlier, there have been some analytical approaches for calculating these critical values, which are always prone to the availability of direct analytical equations for each and every case. In this paper, we explored a numerical based technique called the advanced worst-case method to track down the critical parameter set. The worst-case method taken up in this work is capable of accurately and efficiently calculating the critical values in diverse scenarios. The concept has been validated on a comprehensive distributed crosstalk fault model that considers RLGC parameters, coupling parameters together with the strengths of the driver and the receiver.

Modeling of crosstalk fault in defective interconnects

The manufacturing defect in the interconnect lines can lead to various electrical faults, e.g. defect due to under-etching effect/conductive particle contamination on interconnect line can lead to increased coupling capacitances between the two adjacent interconnects, which, in turn, can eventually result in crosstalk fault in the DSM chips. In this paper we describe the line defect-based-crosstalk fault model that will be helpful in analyzing the severity of the defect/fault, as the crosstalk fault occasionally leads to various signal integrity losses, such as timing violation due to excessive signal delay or speed-up, logic failure due to crosstalk positive/negative glitch above/below logic low/high threshold and also reliability problem particularly due to crosstalk glitch above logic high threshold. Our crosstalk fault model accuracy is very close to PSPICE simulation results when the defect/fault is located in the middle of interconnects, whereas for the defects located at the near-end/far-end side of aggressor-victim the model accuracy differs approximately by ±5% respectively.