Akihiko Kato

An 83dB-dynamic-range single-exposure global-shutter CMOS image sensor with in-pixel dual storage

CMOS image sensors with rolling exposure have come to be widely used, but they cannot avoid the distortion inherent to rolling exposure no matter how much exposure speed improves for capturing a moving target. The need has consequently been felt for global-shutter CMOS image sensors.

An 8.3M-pixel 480fps global-shutter CMOS image sensor with gain-adaptive column ADCs and 2-on-1 stacked device structure

A 4K2K 480 fps global-shutter CMOS image sensor has been developed with super 35 mm format. This sensor employs newly developed gain-adaptive column ADCs to attain a dark random noise of 140 μVrms for the full-scale readout of 923 mV. An on-chip online correction of the error between two switchable gains maintains the nonlinearity of output image within 0.18 %. The 16-channel output interfaces with 4.752 Gbps/ch are implemented in 2 diced logic chips stacked on a sensor chip with 38K micro bumps.

8.3 M-Pixel 480-fps Global-Shutter CMOS Image Sensor with Gain-Adaptive Column ADCs and Chip-on-Chip Stacked Integration

This paper presents a 4K2K 480-fps global-shutter CMOS image sensor with a super 35-mm format for a highly realistic digital video system. The sensor employs newly developed gain-adaptive column analog-to-digital converters to obtain input-referred dark random noise of 140

Solid-state image pickup apparatus, signal processing method for a solid-state image pickup apparatus, and electronic apparatus

mu text{V}_{mathrm {rms}}

Solid-state imaging device and driving method as well as electronic apparatus

for an input-referred full-scale readout of 923 mV. An on-chip online correction of the error between two switchable gains maintained the nonlinearity of the output image within 0.18%. A chip-on-chip integration process realized a front-illuminated image sensor stacked with two diced logic chips through 38-K microbump interconnections. The global-shutter pixel achieved a parasitic light sensitivity of −99.6 dB. The 16-channel output interfaces with 4.752 Gbps/ch were implemented in the stacked logic chips.