Tadayuki Taura

Design of a sense circuit for low-voltage flash memories

A new sense circuit directly sensing the bitline voltage is proposed for low-voltage flash memories. A simple reference voltage generation method and a dataline switching method with matching of the stray capacitance between the dataline pairs are also proposed. A design method for the bitline clamp load transistors is described, taking bitline charging speed and process margins into account. The sense circuit was implemented in a 32-Mb flash memory fabricated with a 0.25-/spl mu/m flash memory process and successfully operated at a low voltage of 1.5 V.

A channel-erasing 1.8 V-only 32 Mb NOR flash EEPROM with a bit-line direct-sensing scheme

A 1.8 V-only 32 Mb NOR flash EEPROM uses a channel-erasing scheme for the 0.49 /spl mu/m/sup 2/ cell in 0.25 /spl mu/m CMOS technology. The block decoder circuit with an erase-reset sequence performs channel-erase. The bit line direct sense permits sub-1.8 V operation, suitable for use in handheld systems.A 1.8-V-only 32-Mb NOR flash EEPROM has been developed based on the 0.25-/spl mu/m triple-well double-metal CMOS process. A channel-erasing scheme has been implemented to realize a cell size of 0.49 /spl mu/m/sup 2/, the smallest yet reported for 0.25-/spl mu/m CMOS technology. A block decoder circuit with a novel erase-reset sequence has been designed for the channel-erasing operation. A bitline direct sensing scheme and a wordline boosted voltage pooling method have been developed to obtain high-speed reading operation at low voltage. An access time of 90 ns at 1.8 V has been realized.

Wordline voltage generating system for low-power low-voltage flash memories

A low-power wordline voltage generating system is developed for low-voltage flash memories. The limit for the stand-by current including the operation current for the band-gap reference and the stand-by wordline voltage generator is discussed. The system was implemented on a 1.8-V 32-Mb flash memory fabricated with a 0.25-/spl mu/m flash memory process and achieved with very low stand-by current of 2 /spl mu/A typically, and high operating frequency of 25 MHz in read operation at 1.8 V. A low-voltage level shifter with high-speed switching is also proposed.

A 44-mm/sup 2/ four-bank eight-word page-read 64-Mb flash memory with flexible block redundancy and fast accurate word-line voltage controller

Combining a negative-gate channel-erasing NOR flash memory technology with an aggressively-scaled NAND flash process technology results in a 64 Mb NOR flash memory with 0.27 /spl mu/m/sup 2/ cell and 44 mm/sup 2/ chip. The flash memory provides 4 independent banks for flexible dual operation and unique block redundancy for yield.