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Dive into the research topics where Akihiro Tsutsui is active.

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Featured researches published by Akihiro Tsutsui.


field programmable gate arrays | 1997

YARDS: FPGA/MPU hybrid architecture for telecommunication data processing

Akihiro Tsutsui; Toshiaki Miyazaki

This paper presents a novel system architecture applicable to high-performance and flexible transport data processing which includes complex protocol operation and a nehvork control algorithm. We developed a new tightly coupled Held Programmable Gate Array (FPGA) and Micro-Processing Unit (MPU) system named. Yet Another Re-Definable System (YARDS). It comprises three programmable devices which equateto high flexibility. These devices are the RISC-type MPU with memories, programmable inter-connection devices, and FPGAs. Using these, this system supports various styles of coupling between the FPGAs and the MPU which are suitable for constructing transport data processing. In this paper, two applications of the systemin the telecommunications field are given. One is an Operation, Administration, and Management (OAM) cell operations on an AsynchronousTransfer Mode (ATM) network. The other is a dynamic configuration protocol enables the updateor changeof the functions of the transport data processing system on-line. This is the first approach applying the FPGA/MPU hybrid system to the telecommunications field.


international conference on computer design | 1994

PROTEUS: programmable hardware for telecommunication systems

Naohisa Ohta; Hiroshi Nakada; Kazuhisa Yamada; Akihiro Tsutsui; Toshiaki Miyazaki

This paper discusses a new architecture for programmable hardware targeted at high-speed digital telecommunication systems and describes a preliminary design. The basic architecture of the programmable hardware is proposed based on the characteristics of functions and an analysis of logic used in actual communication subsystems performing high-speed bit level operations. The proposed architecture, called PROTEUS, includes a pipeline structure of logic and latch groups, and a 2-stage logic block structure that consists of small LUTs and wide gates. The design strategy of a prototype chip and the CAD techniques used to achieve the required performance are also discussed.<<ETX>>


international conference on computer design | 1995

Special purpose FPGA for high-speed digital telecommunication systems

Akihiro Tsutsui; Toshiaki Miyazaki; Kazuhisa Yamada; Naohisa Ohta

A new FPGA (Field Programmable Gate Array) is developed for high-speed digital telecommunication systems. As architecture is based on the fundamental characteristics extracted from an analysis of actual systems. The FPGA has several unique features for realizing high-speed transport data processing. It allows us to build the high-performance components that are frequently used in transport data processing. In addition, its inter-chip connection mechanism enables us to build flexible multi-FPGA modules. Furthermore, we introduce a dedicated CAD system for the FPGA. We design several actual transport processing circuits on the FPGA using the CAD system and evaluate them. Experimental results show that the device has the potential to realize practical systems.


field programmable gate arrays | 1998

More wires and fewer LUTs: a design methodology for FPGAs

Atsushi Takahara; Toshiaki Miyazaki; Takahiro Murooka; Masaru Katayama; Kazuhiro Hayashi; Akihiro Tsutsui; Takaki Ichimori; Kennosuke Fukami

In designing FPGAs, it is important to achiev e a good balance bet w een the number of logic blocks, suc h has Look-Up Tables (LUTs), and wiring resources. It is difficult to find an optimal solution. In this paper, w e presen t an FPGA design methodology to efficiently find well-balanced FPGA architectures. The method covers all aspects of FPGA development from the architecture-decision process to physical implementation. It has been used to develop a new FPGA that can implement circuits that are twice as large as those implementable with the previous version but with half the number of logic blocks. This indicates that the methodology is effectiv e in dev eloping well-balanced FPGAs.


IEEE Transactions on Very Large Scale Integration Systems | 2000

PROTEUS-Lite project: dedicated to developing a telecommunication-oriented FPGA and its applications

Toshiaki Miyazaki; Atsushi Takahara; Takahiro Murooka; Masaru Katayama; Takaki Ichimori; Kazuhiro Shirakawa; Akihiro Tsutsui; Kennosuke Fukami

This paper describes a project dedicated to developing an improved (in terms of usability) version of our previous telecommunication-oriented field programmable gate array (FPGA), and its applications. To achieve this goal, we adopt several challenging design strategies. First, we determine the new FPGA architecture based on a quantitative evaluation carried out to optimize the interaction between the FPGA and CAD algorithms. In addition, we create a new chip design environment that allows semi-automatic test pattern generation and cross-checking between logic and layout design. Furthermore, a dedicated CAD system is developed based on a consideration of the evaluation results and the characteristics of the FPGA. As a result of these design strategies, the FPGA and CAD system are well-balanced, and even though the FPGA has very rich routing resources, the routing process can be finished quickly without sacrificing application-circuit performance. The FPGA is applied to several reconfigurable systems for telecommunications, and is found to offer the required functions and good performance.


field programmable logic and applications | 1997

CAD-oriented FPGA and dedicated CAD system for telecommunications

Toshiaki Miyazaki; Atsushi Takahara; Masaru Katayama; Takahiro Murooka; Takaki Ichimori; Kennosuke Fukami; Akihiro Tsutsui; Kazuhiro Hayashi

This paper describes a newly developed FPGA and its dedicated CAD system. The FPGA is an improved version of our previous telecommunication-based FPGA, especially in terms of the routing resource architecture. Thus, in addition to having the good features of our previous FPGA for realizing telecommunications circuits, it enables us to adopt a top-down design methodology for application circuits configured in the FPGA. The architecture is determined based on a quantitative evaluation carried out to balance the FPGA with CAD algorithms.


IEEE Transactions on Very Large Scale Integration Systems | 1998

ANT-on-YARDS: FPGA/MPU hybrid architecture for telecommunication data processing

Akihiro Tsutsui; Toshiaki Miyazaki

This paper presents a novel system architecture that combines tightly coupled field programmable gate arrays (FPGAs) and a microprocessing unit (MPU) that we have developed. This system architecture comprises three main programmable devices which yield high flexibility. These devices are a reduced instruction set computer (RISC)-type MPU with memories, programmable interconnection devices, and FPGAs. This system supports various styles of coupling between the FPGAs and the MPU which makes several data processing operations more effective. Furthermore, we indicate the most suitable applications for the system. They are telecommunication data processes involving complex protocol operations and network control algorithms. In this paper, two applications of the system are given. One is for operation, administration, and management (OAM) cell processing on an asynchronous transfer mode (ATM) network. The other is a dynamic remote reconfiguration protocol that enables the functions of the transport data processing system to be updated or changed on-line.


IEEE Transactions on Very Large Scale Integration Systems | 1995

Performance improvement technique for synchronous circuits realized as LUT-based FPGAs

Toshiaki Miyazaki; Hiroshi Nakada; Akihiro Tsutsui; Kazuhisa Yamada; Naohisa Ohta

This paper presents a new technique for improving the performance of a synchronous circuit configured as a look-up table based FPGA without changing the initial circuit configuration; only the register location is altered. It improves clock speed and data throughput at the expense of latency. One of the most significant benefits realized by this approach is that the time-consuming and user-uncontrollable reconfiguration processes, i.e., remapping, replacement, and rerouting, are unnecessary when improving circuit performance. After applying our technique to some benchmark circuits, the average performance improvement was 33% for six combinational circuits, and 25% for 18 sequential circuits. >


field programmable logic and applications | 1992

New application of FPGAs to programmable digital communication circuits

Naohisa Ohta; Kazuhisa Yamada; Akihiro Tsutsui; Hiroshi Nakada

This paper proposes a new design method to construct flexible, high performance digital communication systems. The method, called Amphibious Logic, combines top-down design with high level synthesis and reconfigurable hardware. The methods capability and problems that had to be solved associated are discussed. Design examples using the high level CAD system called PARTHENON and conventional FPGAs are illustrated. The results show that it is possible to create programmable, high performance digital communication circuits with the proposed method.


IEICE Transactions on Communications | 2008

Latest Trends in Home Networking Technologies

Akihiro Tsutsui

Broadband access service, including FTTH, is now in widespread use in Japan. More than half of the households that have broadband Internet access construct local area networks (home networks) in their homes. In addition, information appliances such as personal computers, networked audio, and visual devices and game machines are connected to home networks, and many novel service applications are provided via the Internet. However, it is still difficult to install and incorporate these devices and services because networked devices have been developed in different communities. I briefly explain the current status of information appliances and home networking technologies and services and discuss some of the problems in this and their solutions.

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