Takahiro Murooka

4K SHD Real-Time Video Streaming System With JPEG 2000 Parallel Codec

This paper describes a 4K SHD (super high definition) real-time video streaming system that can encode (JPEG 2000), transmit and display live images at up to 4096 times 2160 pixel resolution and 36-bit color. The total bit rate of a 4K SHD video to be shown at 30 frames per second in 4:4:4 format is 9.5 Gbps. A JPEG 2000 parallel codec reduces this to 200-400 Mbps and allows live image distribution via common 1 Gbps links with the highest image quality and minimal delay. This system makes it feasible to implement networked professional audio/video applications over long-distance IP networks even at SHD quality

APE: fast and secure active networking architecture for active packet editing

This paper proposes an architecture for active network nodes, called Active Packet Editing (APE). The design of APE focuses on accelerating the functions that are essential to active network operation, such as packet classification and NAT. The twofold architecture of APE combines a software active packet processor with an efficient packet editor based on flexible hardware. Based on preset rules (pattern, action), the packet editor classifies and modifies, to a limited extent, packets that pass through the node. Upon the receipt of active packets, the software active packet processor dynamically configures the packet editor. To prevent interference among active applications, and thus ensure security, cryptographic techniques are used to distribute a flow specific key string, which is used to authenticate succeeding packets in the same flow. We are developing a prototype APE node.

Beyond 4K: 8K 60p live video streaming to multiple sites

The high definition of 4K motion pictures makes them applicable to a wide variety of purposes. The development of 4K image equipment such as cameras, displays, and playback systems has made easy viewing of 4K video possible. Video frame rates have also become higher, enabling 4K-60 fps progressive (60p) video streams to be transmitted over IP networks. However, problems remain in increasing video image resolution to 8K or more so as to build systems in which many people collaborate at the same time. This paper describes a video transmission system that attains image resolution of 8K-60p or higher by synchronizing multiple 4K transmission systems we have developed. Since 8K-60p transmission over IP networks has extremely high traffic rates, schemes for achieving robust transmission such as forward error correction (FEC) must also have very high rates. We have also developed techniques for attaining reliable transmission, i.e., the use of low-density generator matrix (LDGM) codes to achieve high throughput FEC, application-layer multicasting, and monitoring network status at multiple points.

A Study on the Correlation between QoE of 4K Super High Definition Video Streamings and QoS of Network

Realtime video streaming is one of the most impor- tant tool for the computer supported collaborative workspace (CSCW). CSCW requires bi-directional or many-directional video exchanging. The delay or jitter caused by network quality is easily affecting application or users of CSCW. The quality of experience (QoE) of CSCW with video streaming over IP networks depends on the quality of network. It is important to consider the relationship between the QoE of video streaming and quality of service (QoS) of the network in order to achieve high quality CSCW services effectively. Then we can define the suitable parameter of networks for the applications. The goal of this research is to establish the evaluation method of the correlations between the QoE of CSCWs and QoS of networks to obtain the optimal real-time communication system design. In this paper, we propose a method to measure the correlation between the application and network QoS with precise packet monitoring environment. The result shows that micro-second resolution helps a lot to capture the precise behavior which effects the codec systems performance.

Next-generation home networking and relevant technologies

The next generation home network that will accommodate various services with different quality requirements is introduced. Technical study items for realizing this network are described. Current technologies are overviewed to clarify what will need further consideration.

More wires and fewer LUTs: a design methodology for FPGAs

In designing FPGAs, it is important to achiev e a good balance bet w een the number of logic blocks, suc h has Look-Up Tables (LUTs), and wiring resources. It is difficult to find an optimal solution. In this paper, w e presen t an FPGA design methodology to efficiently find well-balanced FPGA architectures. The method covers all aspects of FPGA development from the architecture-decision process to physical implementation. It has been used to develop a new FPGA that can implement circuits that are twice as large as those implementable with the previous version but with half the number of logic blocks. This indicates that the methodology is effectiv e in dev eloping well-balanced FPGAs.

PROTEUS-Lite project: dedicated to developing a telecommunication-oriented FPGA and its applications

This paper describes a project dedicated to developing an improved (in terms of usability) version of our previous telecommunication-oriented field programmable gate array (FPGA), and its applications. To achieve this goal, we adopt several challenging design strategies. First, we determine the new FPGA architecture based on a quantitative evaluation carried out to optimize the interaction between the FPGA and CAD algorithms. In addition, we create a new chip design environment that allows semi-automatic test pattern generation and cross-checking between logic and layout design. Furthermore, a dedicated CAD system is developed based on a consideration of the evaluation results and the characteristics of the FPGA. As a result of these design strategies, the FPGA and CAD system are well-balanced, and even though the FPGA has very rich routing resources, the routing process can be finished quickly without sacrificing application-circuit performance. The FPGA is applied to several reconfigurable systems for telecommunications, and is found to offer the required functions and good performance.

CAD-oriented FPGA and dedicated CAD system for telecommunications

This paper describes a newly developed FPGA and its dedicated CAD system. The FPGA is an improved version of our previous telecommunication-based FPGA, especially in terms of the routing resource architecture. Thus, in addition to having the good features of our previous FPGA for realizing telecommunications circuits, it enables us to adopt a top-down design methodology for application circuits configured in the FPGA. The architecture is determined based on a quantitative evaluation carried out to balance the FPGA with CAD algorithms.

Transmutable telecom system and its application

The paper describes a transmutable telecom system called ATTRACTOR, which uses more than 100 FPGAs, and features both reconfigurability and high performance. There are two key innovations. One is the board-level modularity concept that allows different functions to be implemented on different boards individually. The other is a high-speed serial link mechanism that provides excellent inter-board communication without sacrificing performance. Thus this system can be completely reconstructed to suit different applications by arranging different board combinations and reconfiguring each board. Using ATTRACTOR, we realized an IP packet forwarder, which is very speed-intensive telecom function, that has to decide the next-hop address of each incoming IP packet and send it out on-the-fly. It was confirmed that the function works well in a real ATM-LAN environment.

Real-time packet editing using reconfigurable hardware for active networking

An active network node architecture, called Active Packet Editing (APE), is proposed. The main concept of APE is to accelerate functions essential to active network operation, such as packet classification and NAT (Network Address Translation). The twofold architecture of APE combines a software active packet processor with a high-speed hardware packet editor. Based on preset rules (pattern, action), the packet editor classifies and modifies packets passing through the node. Upon the receipt of active packets, the software active packet processor dynamically configures the packet editor. This paper focuses on introducing the high-speed packet editing mechanism which utilizes FPGAs (Field Programmable Gate Arrays) and CAMs (Content Addressable Memories). A prototype network node based on the architecture performs Gigabit-class throughput with packet editing.