Akinobu Shibuya

Si interposers integrated with SrTiO 3 thin film decoupling capacitors and through-Si-vias

Si interposers with SrTiO3 (STO) thin film capacitors and their stacking process based on chip-to-wafer bonding have been developed. To reduce defect density in chip-size capacitors, the STO thin films were sputter-deposited at 400degC, and Ru was used as a bottom electrode. The stacking process enables the 50-mum-thick Si interposers to be inserted between an LSI and a board. Maximum capacitance density of 2.5 muF/cm2 was obtained for 60-nm-thick STO capacitors in an area of 20 mm times 20 mm with 9000 through-silicon-vias (TSVs). Capacitance for the LSI/Si interposer stacks with 1 muF and 1600 TSVs did not change during a thermal cycle test up to 1000 cycles.

New MCM composed of D/L base substrate, high-density-wiring CSP and 3D memory modules

A RISC (reduced instruction set computer) module, which contains secondary cache memories and is called an MCM for use in a high-performance workstation has been developed. The design consists of a D/L (deposited organic thin film on laminated printed-circuit board) base substrate, a glass-ceramic-based organic-thin-film multilayer build-up CSP (chip size package), and glass-ceramic 3-dimensional memory (3DM) modules. The characteristics of this newly developed MCM are as follows. The D/L base substrate has 179 I/O (input/output) pins and signal lines of 25-/spl mu/m width and 50-/spl mu/m pitch. The CSP carrier signal lines are as fine as those of the D/L, and the CSP carrier features 525 I/O pads and 80-/spl mu/m diameter chip bonding pads with 108-/spl mu/m pitch. The 3DM is almost the same size as a conventional single chip mold package; with the stacking of ten memory chips in the space of four 3DMs, the area required is roughly only that of four single chip packages.

A Silicon Interposer With an Integrated

A silicon interposer with an integrated with SrTiO3 (STO) thin film capacitor that decreases switching noise in high-speed digital circuits has been developed, along with a process to fabricate it. The process for fabricating the capacitor was optimized to reduce the defect density. The identified optimal process conditions are sputter-depositing the STO at 400 °C and using Ru as a bottom electrode. An large-scale integration chip is stacked on the Si interposers using chip-to-wafer bonding, and through-silicon vias (TSVs) are then formed in the interposer. This stacking enables a 50 μm-thick Si interposer to be inserted between a chip and a printed wiring board (PWB). A maximum capacitance density of 2.5 F/cm2 was achieved for a 60-nm-thick STO capacitor in a 20 × 20 mm2 area with 9000 TSVs (50- diameter; 50- depth). The capacitance of slightly more than 1 F in interposer-chip stack samples with 1600 TSVs remained constant during a thermal testing on PWBs for up to 1000 cycles.

{\rm SrTiO}_{3}

Novel SrTiO/sub 3/-based flexible and thin capacitors with total thickness of only 40 /spl mu/m have been developed as decoupling capacitors. The sputter-deposited SrTiO/sub 3/ thin film capacitors, with electroplated Cu terminals, are fabricated on polyimide-coated Si substrates using photolithography and thin film process technologies. The capacitor parts, including polyimide, are finally peeled off from the Si substrates. Manganese impurity doping into the SrTiO/sub 3/ is effective for good uniformity and low temperature deposition down to 250/spl deg/C. A highly elastic molybdenum film, as a part of the bottom electrodes, successfully suppresses the polyimide contraction during SrTiO/sub 3/ deposition up to 400/spl deg/C. The diced flexible capacitor shows a large capacitance density of 3.2 nF/mm/sup 2/, and low leakage current of 10/sup -7/ A/cm/sup 2/ at 10 V.

Thin Film Decoupling Capacitor and Through-Silicon Vias

Pb(Zr,Ti)O3 (PZT) thin film has been crystallized at below 450°C by means of a sol–gel process that employs a PT-seeding method, and it has been used to fabricate a PZT thin-film capacitor on polyimide film at a high decomposition temperature. The capacitor structure includes a 4-layer bottom electrode: Pt(200 nm)/Ti(50 nm)/Mo(600 nm)/Ti(50 nm). Capacitance density is 12 nF/mm2 in the effective capacitance area. Despite the use of PZT, a high-k material, this thin-film capacitor still offers high insulation resistance (6.2 GΩ at 3 Vdc) and reliability sufficient for use as a decoupling capacitor.

Novel flexible and thin capacitors with Mn-doped SrTiO/sub 3/ thin films on polyimide films

Integral passive components provide efficient circuit miniaturization while maintaining high performance and reducing assembly costs. The development of practical integral passive components, however, requires advances in the areas of materials, low-cost processes, and structural design. We have developed new TiNxOy thin-film resistors, as well as a termination resistor-embedded CSP, and a process for fabricating integral passive components. Our TiNxOy films exhibit a sheet resistivity in the range of 30-5k /spl Omega//square. To keep costs low, we have made the fabrication process compatible with that for MCM-D/L. Resistors as small as 25 /spl mu/m square have been successfully produced with this process. The chip scale package (CSP) with embedded resistors has been designed for 10 Gbps optical transmitter and receiver modules. A fabricated version shows excellent return loss for its termination resistor, less than -20 dB in the frequency range of 50 MHz-14 GHz, and its resistors showed high reliability in constant voltage stress tests, with less than 5% change in resistance at 800 mW/mm/sup 2/ over 1000 hours.

High-Capacitance Thin-Film Capacitors on a Polymer Film

In this report, mineral composition of rock samples including conglomerate, sandstone, and dolomite was analyzed by IR spectral imaging using QDIP focal plane arrays (FPAs) with a peak-responsivity wavelength of 6.5 μm (FPA 1) and 5.5 μm (FPA 2). The qualitative and quantitative analyses are presented, and the key factor that determines the quantitative precision is discussed. In the qualitative analysis, the luminance of the different components in the rock samples was compared in the image. In the FPA 1 images, the shell fossil in the conglomerate sample and the limestone in the sandstone sample were darker than the other parts of the rocks due to their low emittance at 6.5 μm. In contrast, the difference in the luminance is hardly observed in the FPA 2 images under the same conditions. In the quantitative analysis, the emittance of dolomite was measured. Ten points in the IR image were randomly selected and the average emittance was calculated. The obtained emittances were 0.544±0.012 (FPA 1) and 0.941±0.019 (FPA 2), which means the coefficient of variation of the emittance measurement is ±2.1%~2.2%. By calculating the propagation of error, the precision of thermocouples for monitoring the temperature of the rocks in the calibration contributes most significantly (73%) to the total error.