Akira Kanuma

CMOS circuit optimization

Abstract In this paper, optimization algorithms for CMOS circuits are described, from the propagation delay time viewpoint. The propagation delay time for a CMOS in erter is calculated for a step function input. A classical model of I–V characteristics for a MOSFET and the worst case Sah model for inter-electrode capacitances of a MOSFET are used for this deduction.

TX Series Based on TRONCHIP Architecture

The general development philosophy is described for our TX series which consists of a basic core processor, higher performance ones and superintegrated autonomous derivative processors. All these processors are designed on the single TRONCHIP architecture. The core processor TX1 is designed to be widely used for controllers of highly intelligent machines. The TX1 pipeline structure and its performance simulation are discussed intensively, which endorse more than five MIPS. The higher performance processor TX3 contains a memory management unit and 16K byte cache memory on chip and achieves over ten MIPS including basic floating-point instructions. As the first example of TX series superintegration, an organization of LAN processor is discussed which integrates a Token.Ring controller logic, high speed RAM and TX1 as a network processor. Lastly, our basic idea is described for the application support systems which include a real-time OS nucleus.

1.65 Gb/s 60 mW 4:1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs using 2 V 3-level series-gating ECL circuits

The 1.65 Gb/s 60 mW 4:1 multiplexer and 1.8 Gb/s 80 mW 1:4 demultiplexer ICs in a 1.2 /spl mu/m, 15 GHz bipolar process operate with a -2 V single power supply, and exhibit the lowest power-delay products reported to date. Low dissipation results from ECL circuit techniques enabling three-level series gating with a 2 V supply.

A CMOS 510 K-transistor single-chip token-ring LAN controller (TRC) compatible with IEEE802.5 MAC protocol

The token-ring controller (TRC) consists of five functional blocks. they are a dedicated 16-b microprocessor which includes 11 K-word*20-b protocol firmware ROM, finite-state machines for real-time handling of frames, an 896-word*16-b dual-port RAM for frame buffer FIFOs and working memory (FIFO/RAM), a host processor bus interface, and a three-channel DMA controller which can follow list structure frame buffers. The TRC interprets and executes 16 types of commands and handles 23 types of media access control (MAC) frames. It can continuously receive more than 90% of incoming packets with 64-byte information length at 40 Mbit/s network speed. It is fabricated with double-metal-layer 1.2- mu m CMOS technology and integrates 510 K MOSFETs in a 14.49-mm*14.62-mm chip area. The maximum power consumption is 0.945 W at 8-MHz operating frequency and 5-V+or-5% power supply low-power systems but also for high-performance applications. >

A 20MHz 32b pipelined CMOS image processor

A 32b image processor with writable control stores that can process a 1024-point complex FFT in 1ms, has been developed. This paper will report on features which include fabrication in 1.2μm N-well CMOS, use of double layer metal technology and the integration of 170K transistors. Dissipation is 750mw at 5V.