Akira Onozawa

Arm-Pointer: 3D Pointing Interface for Real-World Interaction

We propose a new real-world pointing interface, called Arm-Pointer, for user interaction with real objects. Pointing at objects for which a computer is to perform some operation is a fundamental, yet important, process in human-computer interaction (HCI). Arm-Pointer enables a user to point the computer to a real object directly by extending his arm towards the object. In conventional pointing methods, HCI studies have concentrated on pointing at virtual objects existing in computers. However, there are the vast number of real objects that requires user operation. Arm-Pointer enables users to point at objects in the real world to inform a computer to operate them without the user having to wear any special devices or making direct contacts with the objects. In order to identify the object the user specifies, the position and direction of the arm pointing are recognized by extracting the user’s shoulders and arms. Therefore, an easy-to-use real-world oriented interaction system is realized using the proposed method. We developed an algorithm which uses weighted voting for robust recognition. A prototype system using a stereo vision camera was developed and the real-time recognition was confirmed by experiment.

A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design

A regenerator-section terminating digital large-scale-integration chip for an STM-16 (2.5-Gbit/s synchronous optical network/synchronous digital hierarchy) regenerator has been developed using low-power bipolar technologies. The high-speed performance of bipolar devices enabled four or more chips, including a demultiplexer and a multiplexer, to be integrated into a single chip. The low-power dissipation of 557 mW, only about one-tenth that of previously reported chips, was achieved through the use of four design steps: one-chip integration architecture, power management, 2.5-V emitter-coupled logic, and power optimization.

Post-layout optimization of power and timing for ECL LSIs

An optimization algorithm for power and timing of bipolar ECL LSls is proposed. The power dissipation is minimized by a nonlinear programming solver under accurate timing constraints extracted from layout. The power and delay time of an ECL gate are considered functions of its switching current which is regulated by programming its resistors. Experimental results show significant power reductions for circuits including a real chip without degrading the performance.<<ETX>>

High-speed, low-power, bipolar standard cell design methodology for Gbit/s signal processing

A low-power Si bipolar standard cell LSI design methodology for gigabit/second signal processing is described. To obtain high-speed operation, it features a pair of differential clock channels inside cells, differential clock distribution with the placement of differential wires of equal length and load, a performance-driven layout, and a highly accurate static timing analysis. A computer-aided-design-based optimization technology for power dissipation makes cell currents minimum while maintaining the circuit speed. A 5.6-K gate synchronous digital hierarchy signal-processing LSI operating at 1.6 Gbit/s with only 3.9 W power consumption demonstrates the effectiveness of this design method.

Representation of Pseudo Inter-reflection and Transparency by Considering Characteristics of Human Vision

We have succeeded in developing a quick and fully automated system that can generate photo‐realistic 3D CG data based on a real object. A major factor in this success comes from our findings through psychophysical experiments that human observers do not have an accurate idea of what should be actually reflected as inter‐reflections on the surface of an object. Taking advantage of this characteristic of human vision, we propose a new inter‐reflection representation technique in which inter‐reflections are simulated by allowing the same quantity of reflection components as there are in the background to pass through the object. Since inter‐reflection and transparency are calculated by the same algorithm, our system can capture 3D CG data from various real objects having a strong inter‐reflection, such as plastic and porcelain items or translucent glass and acrylic resin objects. The synthetic images from the 3D CG data generated with this pseudo inter‐reflection and transparency look very natural. In addition, the 3D CG data and synthetic images are produced quickly at a lower cost.

A balanced-mesh clock routing technique using circuit partitioning

A clock routing technique using a balanced-mesh routing is proposed, which incorporates the advantages of both the well-known balanced-tree and fixed-mesh routing method. The circuit is partitioned into subblocks called Mesh-Routing Regions (MRs) in which clock skew is suppressed below a constant by mesh routing. Then the net from the clock source to each MR is routed as a balanced-tree. In using the technique to design an MPEG2-encoder LSI, a skew of 210 ps was achieved.

A novel hardware algorithm for real-time image recognition based on real AdaBoost classification

Real-time object detection is important for surveillance applications. This paper describes a high-performance object detector using a commercially available FPGA. Major bottlenecks in the real AdaBoost classifier are resolved. A new FIR-filter-like hardware architecture takes advantage of an FPGAs hardware parallelism and block-RAM structure. The resulting design uses Xilinx Virtex 5 and achieves the real-time processing performance of 220 f/s at 201 MHz and adjustable recognition performance with a variable number of weak classifiers. This is the first demonstration of a histogram of oriented gradients and Real AdaBoost detector on an FPGA.

A heuristic algorithm for reducing system-level test vectors with high branch coverage

We introduce a heuristic that generates as few a number of test vectors as possible with high branch coverage for the functional verification of digital design. The challenge is how to save time and effort for sufficient verification at system-level. We focus on generating test vectors from the circuit specification written in C. We reuse them to SystemC description by removing their redundancies while maintaining the branch coverage as is. Experimental results of our practical design show that over 90% on average of the redundant test vectors were reduced with 100% branch coverage maintained. The reused test vectors for SystemC Bus Cycle Accurate models scored 80% branch coverage on average. These results are significant for saving verification cost and beneficial for simplifying debugging works.

An efficient paired-net routing algorithm for high-speed bipolar LSIs

This paper proposes an efficient paired-net routing algorithm. A paired net consists of two nets assigned to adjacent tracks and columns. The paired-net routing approach is applied for differential drive nets in a bipolar ECL LSI to decrease signal skew and enhance signal integrity. Paired nets can cause a new type of cyclic constraint, which does not appear in the conventional vertical constraint graph. To wire these paired nets, the new type of cyclic constraint must be detected and resolved. We applied our approach to two actual bipolar ECL circuits: a 4.0-k-gate circuit, which operated at 3 Gbit/s, and a 5.6-k-gate circuit, which operated at 2.5 Gbit/s. The experimental results verify the effectiveness of our paired-net routing approach.

A novel BMNoC configuration algorithm utilizing communication volume and locality among cores

Network-on-chip (NoC) architectures are emerged as a promising solution to the lack of scalability in multiprocessor systems-on-chips (MPSoCs). In this paper, we propose a novel BMNoC configuration algorithm together with simulation results. Our BMNoC configuration algorithm analyses the data traffic of the target application and determines which core is the right one to put into the certain cluster with its communication volume and locality. Furthermore, the simulation results illustrate the better latency than earlier studies and feasibility of BMNoC.