Haruhiko Ichino

Very-high-speed Si bipolar static frequency dividers with new T-type flip-flops

This paper presents two circuit techniques for highspeed operation of a master-slave toggle flip-flop circuit (MSTFF). One circuit reduces the gain in latching circuits, and the other uses the transient current of the emitter followers to boost the switching speed. Both the SPICE simulations and the measured results for static 1/8 frequency dividers fabricated using 0.5-/spl mu/m super self-aligned process technology (SSTIC) show that the maximum operating speed of our MS-TFFs is 10% and 30% faster than that of conventional ones. By applying these technologies, 19.1-GHz and 22.4-GHz Si bipolar static frequency dividers have been fabricated. >

Over-10-Gb/s IC's for future lightwave communications

This paper reviews research and development in NTT Laboratories on ICs faster than 10 Gb/s for future optical communication systems. Novel design and circuit techniques achieve such high-speed ICs and stable operation even in packages and modules. High-bit-rate operation of 10 Gb/s (10-GHz equalizing amplifier circuit, a 10-GHz clock recovery circuit, 10-Gb/s decision circuits, and 10-Gb/s multiplexers and demultiplexers) is obtained. 20-Gb/s operation is also achieved for some ICs. Future improvements using advanced device and circuit technologies are discussed, and bit rates over 40 Gb/s are predicted. >

A high-speed, low-power bipolar digital circuit for Gb/s LSI's: current mirror control logic

A novel low-power bipolar circuit for Gb/s LSIs, current mirror control logic (CMCL), is described. To reduce supply voltage and currents, the current sources of emitter-coupled-logic (ECL) series gate circuits are removed and the lower differential pairs are controlled by current mirror circuits. This enables circuits with the same function as two-stacked ECL circuits to operate at supply voltage of -2.0 V and reduces the current drawn through the driving circuits for the differential pairs to 50% of the conventional level shift circuits (emitter followers) in ECL. This CMCL circuit achieves 3.1-Gb/s (D-FF) and 4.3-GHz (T-FF) operation with a power supply voltage of -2.0 V and power dissipation of only 1.8 mW/(FF).

A 2.5-Gb/s clock and data recovery IC with tunable jitter characteristics for use in LANs and WANs

A 2.5-Gb/s monolithic clock and data recovery (CDR) IC using the phase-locked loop (PLL) technique is fabricated using Si bipolar technology. The output jitter characteristics of the CDR can be controlled by designing the loop-gain design and by using the switched-filter PLL technique. The CDR IC can be used in local-area networks (LANs) and in long-haul backbone networks or wide-area networks (WANs). Its power consumption is only 0.4 W. For LANs, the jitter generation of the CDR when the loop gain is optimized is 1.2 ps (0.003 UI). The jitter characteristics of the CDR optimized for WANs meet all three types of STM-I6 jitter specifications given in ITU-T Recommendation G.958. This is the first report on a CDR that can be used for both LANs and WANs. This paper also describes the design method of the jitter characteristics of the CDR for LANs and WANs.

Loop-parameter optimization of a PLL for a low-jitter 2.5-Gb/s one-chip optical receiver IC with 1: 8 DEMUX

A loop parameter optimization method for a phase-locked loop (PLL) used in wide area networks (WANs) is proposed as a technique for achieving good jitter characteristics. It is shown that the jitter characteristics of the PLL, especially jitter transfer and jitter generation, depend strongly on the key parameter /spl zeta//spl omega//sub n/ (/spl zeta/ is a damping factor and /spl omega//sub n/ is the natural angular frequency of the PLL), and that the optimization focusing on the /spl omega//sub n/ dependence of the jitter characteristics make it possible to comprehensively determine loop parameters and loop filter constants for a PLL that will fully comply with ITU-T jitter specifications. Using the optimization method with the low-jitter circuit design technique, a low-jitter and low-power 2.5-Gb/s optical receiver IC integrated with a limiting amplifier, clock and data recovery (CDR), and demultiplexer (DEMUX) is fabricated using 0.5-/spl mu/m Si bipolar technology (f/sub T/ = 40 GHz). The jitter characteristics of the IC meet all three types of jitter specifications given in ITU-T recommendation G.783. In particular, the measured jitter generation is 3.2 ps rms, which is lower than that of an IC integrated with only a CDR in our previous work. In addition, the pull-in range of the PLL is 50 MHz and the power consumption of the IC is only 0.68 W (limiting amplifier: 0.2 W, CDR (PLL): 0.3 W, DEMUX: 0.18 W) at a supply voltage of -3.3 V and only 0.35 W at a supply voltage of -2.5 V (without output buffers).

12-Gb/s decision circuit IC using AlGaAs/GaAS HBT technology

A decision circuit (DEC) that operates at speeds above 10 Gb/s and utilizes self-aligned AlGaAs/GaAs HBT (heterostructure-bipolar-transistor) technology is described. A DEC consists of a preamplifier, an internal buffer, a D-latch, and an output buffer. In a conventional DEC without an internal buffer, the output level of the high-gain amplifier does not match the logic level of the D-latch. This problem is particularly acute for AlGaAs/GaAs HBT devices because of the dependence of f/sub T/ on V/sub ce/. To overcome this problem, an internal buffer constructed with an emitter-coupled-logic (ECL) gate has been inserted to adjust the amplifier output level to the logic level of the D-latch. The D-latch uses an ECL series-gating technique. The logic swing is 500 mV to enhance speed. The output buffer consists of a differential circuit and is capable of driving 50 loads with 1 V using open-collector circuitry. The reference voltage was generated on the chip. The power consumption is 750 mW with 7.0-V supply.<<ETX>>

A 557-mW, 2.5-Gbit/s SONET/SDH regenerator-section terminating LSI chip using low-power bipolar-LSI design

A regenerator-section terminating digital large-scale-integration chip for an STM-16 (2.5-Gbit/s synchronous optical network/synchronous digital hierarchy) regenerator has been developed using low-power bipolar technologies. The high-speed performance of bipolar devices enabled four or more chips, including a demultiplexer and a multiplexer, to be integrated into a single chip. The low-power dissipation of 557 mW, only about one-tenth that of previously reported chips, was achieved through the use of four design steps: one-chip integration architecture, power management, 2.5-V emitter-coupled logic, and power optimization.

A jitter suppression technique for a 2.48832-Gb/s clock and data recovery circuit

This paper describes a jitter suppression technique for a 2.48832-Gb/s clock and data recovery (CDR) circuit that uses a phase-locked loop (PLL). This technique decreases the jitter generation and improves the jitter transfer function. Jitter generation is suppressed by boosting the loop gain in the PLL. A suitable jitter transfer function and jitter tolerance is achieved by using a low-center-frequency (f/sub c/) surface acoustic wave (SAW) filter. The fabricated circuit has low jitter generation [about 2.4 mUI rms (below 1 ps rms)] and a low cutoff frequency of the jitter transfer function (about 500 kHz) as a result of using a SAW filter with a f/sub c/ of 622.08 MHz. The jitter generations are within 5 mUI rms (2 ps rms) for the temperature range of 0 to 90/spl deg/. The circuit exceeds the jitter tolerance specifications in the International Telecommunication Union (ITU-T) recommendation G.958 by more than 30%.

20 Gb/s digital SSIs using AlGaAs/GaAs heterojunction bipolar transistors for future optical transmission systems

Design principles for achieving good eye opening and circuit optimization to extract high performance from AlGaAs/GaAs heterojunction bipolar transistor (HBT) devices are described. Using the circuit techniques and HBTs with an f/sub T/ of 70 GHz and an f/sub max/ of 50 GHz, four kinds of SSIs are developed for future optical transmission systems. High-bit-rate operation of over 20 Gb/s (26 GHz toggle flip-flop, 20 Gb/s decision circuit, 20 Gb/s EXCLUSIVE OR/NOR gate, and 28 Gb/s selector IC), extremely fast rise and fall times (20-80%) of 20 and 14 ps, respectively, and good eye opening are obtained. In addition, potential performance gains that might be realized through advanced circuit and device design are appraised, and throughputs as fast as 40 Gb/s are predicted. >

An ultracompact, 2-cc-size, 0.64-W 2.5-Gbit/s optical receiver module combined with an MU receptacle

Summary form only given. Recently, optical communication systems have been applied to various field such as local area networks (LANs), optical interconnections, SDH/SONET, and wavelength-division multiplexing (WDM) systems. To achieve these systems cost-effectively, some trials have been made to realize low-power and small-size optical modules. We have developed an ultra-compact and low-power 2.5-Gbit/s optical receiver (OR) module based on a novel structure and advanced IC design. For drastic size reduction, we used the following design schemes: (1) a butterfly package merged with an MU receptacle (MU-R), (2) multichip module (MCM) technology for assembling ICs, and (3) advanced IC design to eliminate external components that obstruct size reduction.