Akira Yamaga

A 7uW deep-sleep, ultra low-power WLAN baseband LSI for mobile applications

Low power IEEE 802.11n single input single output (SISO) wireless LAN (WLAN) baseband LSI has been developed for mobile applications. The multiple low power technologies such as on-chip power gating and high throughput technologies for expanding idle time are applied to the LSI. By minimizing always-on circuits and implementing them using thick gate-oxide transistors, 7uW stand-by power consumption is achieved with negligible shutdown/restart transition time. The built-in wake-up timer and on-chip CPU enables continuous transmit/receive operation without an external intervention.

A software oriented modem architecture for 3G terminal

In this paper we discuss a software oriented modem LSI. At first, the target system is focused on 3GPP DS-FDD mode and signal processing complexity of the developed software simulator is measured. According to the signal processing requirement, modem functions are partitioned into hardware and software. At the same time, a layered modem architecture which is a kind of multiprocessor architecture is proposed. This architecture can perform parallel processing by plural CPU cores, and therefore, it can lower the CPU clock and make software simple. We consider the support service switching possibility for further discussion. Moreover we have developed an evaluation board system. Referring to the implementation results, we discuss hardware complexity and the amount of memory from the viewpoint of LSI development.