Yukimasa Miyamoto

A 9.7mW AAC-Decoding, 620mW H.264 720p 60fps Decoding, 8-Core Media Processor with Embedded Forward-Body-Biasing and Power-Gating Circuit in 65nm CMOS Technology

A AAC-decoding, H.264 decoding, media processor with embedded forward-body-biasing and power-gating circuit in CMOS technology is proposed. Since all the components necessary for the scheme are simple MOS circuits requiring no extra supply voltages, they can be placed and routed by a commercial CAD tool. A data-mapping flip-flop was proposed as a high performance and low-power flip-flop. It is concluded that the power dissipation in H.264 720p 60fps decoding of 620mW at the process fast corner is the lowest among the processor-based solutions.

A UHS-II SD card controller with 240MB/s write throughput and 260MB/s read throughput

This paper presents a UHS-II SD card controller with 240MB/s write and 260MB/s read throughput. Two opposite direction IO lanes for down- and up-streams are quickly switched as single direction for double data rate, without adding extra IO pins. The proposed clock data recovery (CDR) logic can detect symbols within 20ns and minimizes this lane switching overhead. The developed SLVS-type driver that can reduce the common to differential return loss by 15dB is also introduced to improve the noise tolerance.

A low-power multi-core media co-processor for mobile application processors

A multi-core co-processor for mobile application processors is introduced. It provides low-power, high-throughput, fully software-based acceleration of multimedia processing. The test chip fabricated in a 65nm CMOS technology consumes 620mW in H.264 720p 60fps decoding and 9.7mW in MPEG-4 AAC decoding. In the maximum workload of H.264 decoding, a symmetrical parallelization achieves 7.5× performance enhancement by 8 cores. The shared L2 cache reduces the required rate of main memory access to 310MB/s. In the minimum workload of AAC decoding, three low-power circuit techniques reduce 98% of leakage. On-chip regulators, which also work as power-gating switches, lower the supply voltage of processing cores. Embedded forward body-biasing circuit reduces Vt variations. A low-power and fast data-mapping F/F relaxes the timing constraint, which enables a reduction in the number of low-Vt transistors.

A Wireless LAN Baseband LSI for High-Definition A/V Content Transmission

This paper presents the first wireless LAN baseband LSI capable of transmitting high-definition audio with video (HD-A/V) content requiring secure content protection. The LSI fully complies with IEEE 802.11a, e, h, and i. The hybrid coordination function controlled channel access (HCCA) of 802.11e is employed to reserve the transmission period for HD-A/V content. In addition, the block acknowledgement of 802.11e with a forward error correction mechanism is introduced to increase the throughput. Moreover, the digital transmission content protection over the Internet protocol (DTCP-IP) is implemented to prohibit casual copying. High availability of this LSI is provided by two kinds of host interfaces (PCI-bus and HC-bus), an MPEG-2 transport stream interface, and a digital beam forming LSI interface

A software oriented modem architecture for 3G terminal

In this paper we discuss a software oriented modem LSI. At first, the target system is focused on 3GPP DS-FDD mode and signal processing complexity of the developed software simulator is measured. According to the signal processing requirement, modem functions are partitioned into hardware and software. At the same time, a layered modem architecture which is a kind of multiprocessor architecture is proposed. This architecture can perform parallel processing by plural CPU cores, and therefore, it can lower the CPU clock and make software simple. We consider the support service switching possibility for further discussion. Moreover we have developed an evaluation board system. Referring to the implementation results, we discuss hardware complexity and the amount of memory from the viewpoint of LSI development.