Akira Yoshinaka

A Defect Control Technique for the Intrinsic Gettering in Silicon Device Processing

A short period low-temperature-annealing procedure is proposed for the two step annealing process to make effective intrinsic gettering in silicon device processing. A continuous raising of annealing temperature at a constant rate during the low temperature annealing step increases the density of bulk microdefects which are able to grow further in the subsequent high temperature device processing step. The temperature raising rate is limited so that the expanding speed of the critical size of microdefects at the annealing temperature is lower than the growth rate of microdefects. The optimum defect density is discussed from the standpoint of wafer warpage and gettering ability.

Formation of a Stacking Fault-Free Region in Thermally Oxidized Silicon

A stacking fault-free region was found to be formed beneath a Si–SiO2 interface when a silicon crystal was oxidized to generate stacking faults and subsequently annealed in nitrogen atmosphere. This region extends further with prolonged annealing, irrespective of the size and density of the stacking faults already introduced in the crystal. Experimentally it is found that the growth of a stacking fault-free region during annealing follows the equation, d=const. tnexp (-Q/kT) where n and Q are 0.63±0.06 and 4.5±0.6 eV, respectively. The stacking fault nuclei were confirmed to be dissolved after annealing of oxidized crystals.

Relaxation process of interfacial misfit between homoepitaxial silicon crystals

Abstract The relaxation of misfit between epitaxially deposited silicon films and boron-doped silicon substrates by the generation of dislocations has been investigated as a function of the degree of misfit, annealing treatment and the film and substrate thicknesses. For samples with relatively small misfit values, the observed variation of elastic strains remaining in the films as a function of the film thickness is much larger than the equilibrium values predicted by existing theories. In the case of relatively large misfit, however, the measured strains approach the theoretical values as the film thickness increases. These experimental results are discussed by considering the process which impedes the generation of dislocations in the diamond type crystal structures.

The influence of oxidation-sirtl etch condition on the stacking fault generation in (111) silicon wafers

The successive oxidation-Sirtl etch technique has been investigated to evaluate the perfection of silicon crystals by detecting extrinsic stacking faults produced during oxidation. Experiments were performed in (111) epitaxial wafers. Measured densities of stacking faults were found to epend on the conditions of thermal oxidation, and stacking fault densities were a maximum at an oxidation temperature of around 1100°C. The stacking fault densities were reduced appreciably when epitaxial wafers were chemically etched to remove several tens of microns prior to the test. The generation of stacking faults is thought to occur by heterogeneous nucleation due to a very small amount of unidentified impurity found in epitaxial crystals.