Akshaykumar Salimath

Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime

We propose a hetero-gate-dielectric double gate junctionless transistor (HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects of band-to-band tunnelling (BTBT) in the sub-threshold region. A junctionless transistor (JLT) is turned off by the depletion of carriers in the highly doped thin channel (device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel. These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor (n–p–n BJT for channel JLT) in the lateral direction by the source (emitter), channel (base) and drain (collector) regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.

Novel design of combinational and sequential logical structures in quantum dot cellular automata

Quantum dot cellular automata (QCA) is a emerging nanotechnology that promises smaller size and lower power consumption, with faster speed compared to the transistor-based technology. In this paper, we have proposed novel 8-into-3 bit simple encoder, 4-into-2 bit priority encoder, scan flip-flop, and pseudo-random bit sequence generator designs in QCA. These circuits are useful components for the design of many logical and functional circuits. Simulation results of the proposed QCA circuits are obtained by using the QCA designer tool. The correctness of the proposed circuits is hence confirmed.

DESIGN OF A MULTI-LAYERED QCA CONFIGURABLE LOGIC BLOCK FOR FPGAs

In this paper, a Multi-layered configurable logic block (CLB) unit for field programmable gate arrays (FPGAs) is proposed based on quantum-dot cellular automata (QCA) technology. The design is made in multiple layers which help to process information simultaneously, in different layers. Various components of CLB like (4 × 16) Decoder, Memory units, Multiplexers and RS-Flip flops are all designed in multiple layers using higher input majority gates to reduce the cell count and latency compared to previous designs. QCA Designer tool is used to design and simulate the model. The Coherence vector approximation is used for obtaining simulation results.

Role of electron-electron scattering on spin transport in single layer graphene

In this work, the effect of electron-electron scattering on spin transport in single layer graphene is studied using semi-classical Monte Carlo simulation. The D’yakonov-P’erel mechanism is considered for spin relaxation. It is found that electron-electron scattering causes spin relaxation length to decrease by 35% at 300 K. The reason for this decrease in spin relaxation length is that the ensemble spin is modified upon an e-e collision and also e-e scattering rate is greater than phonon scattering rate at room temperature, which causes change in spin relaxation profile due to electron-electron scattering.

Harmonic Performance Evaluation of CMOS SOI SPDT Switch with Embedded Lateral Substrate Model

This paper describes a single pole, double throw (SPDT) CMOS SOI switch in 180nm Technology developed for the GSM 900MHz RF switch applications. Silicon-on-Insulator (SOI) CMOS FETs have many properties which are desirable for RF switch applications. By being manufactured on an insulator substrate, the bulk parasitic capacitances typical of CMOS FETs are eliminated. The SOI FET has a very low Ron-Coff product, allowing for low insertion loss and high isolation in high frequency applications. Despite the low breakdown voltage intrinsic to Si, SOI FETs can be stacked in series to withstand high voltages. This work discuss Harmonic Performance and Power handling behavior of SOI CMOS Switch with non-linear lateral substrate model as a function of gate and body biasing voltages.

Effect of microscopic ripples on spin relaxation length in single-layer graphene

Semiclassical Monte Carlo simulation is used to determine the effect of microscopic ripples on spin relaxation length in freely suspended single-layer graphene. Spin relaxation lengths are simulated using D’yakonov–Perel mechanisms, with comparisons made by including ripple scattering mechanisms along with phonon scattering. The results are simulated with varying temperatures and concentration.

Magnon scattering in single and bilayer graphene intercalates

Semi-classical Monte Carlo simulation is used to determine the effect of magnetic substance as intercalated layer in single layer and bilayer graphene intercalates on spin relaxation length. Spin relaxation lengths are studied with spin density matrix calculation under the effect of one magnon scattering mechanisms. Spin relaxation lengths are simulated and made comparisons by including magnon scattering with phonon scattering. The results are simulated with varying temperatures below Curie temperature.

Simplified 3.3V tolerance circuit for 2.5V I/O design in PCI-X signaling environment

A low voltage interface circuit with a high voltage tolerance enables devices with different power supply levels to be efficiently coupled together without significant leakage current or damage to the circuits. The interface circuit includes an impedance control circuit, an output buffer, an input buffer, an isolation circuit and a pull up protection circuit. When a high voltage is applied to the IO pad, the pull-up protection circuit drives the gate of the pull up transistor to the high IO pad voltage to ensure that no current flows to the positive supply voltage. Also the isolation circuit couples the high IO pad voltage to the body of the pull-up transistor to prevent leakage current through parasitic diodes formed by the pull-up transistor.