Bahniman Ghosh

High-Speed and Low-Power Ultradeep-Submicrometer III-V Heterojunctionless Tunnel Field-Effect Transistor

Tunnel field-effect transistor (TFET) devices are gaining attention because of good scalability and they have very low leakage current. However, they suffer from low ON-current and high threshold voltage. In this paper, we present III-V heterojunctionless TFET (H-JLTFET) for circuit applications. This paper elaborates on interfacing of III-V with group IV semiconductors for heterojunction. Implementing heterojunction and bandgap engineering, we found that devices have significantly improved performance with very high speed even at very low operating voltage. As there is no doping junction present, future scaling could be feasible along with much higher speed of charge carriers than in silicon. GaAs:Si, Si:Si0.3Ge0.7, Si:InAs, and GaAs:Ge, H-JLTFET interface for 20-nm gate length (EOT=2 nm) and dielectric, HfO2 at VGS=1 V and temperature of 300 K have ION of 0.02-12.5 mA/μm, ION/IOFF of 105-1012, and subthreshold swing (average) of 16-74 mV/decade.

Planar junctionless transistor with non-uniform channel doping

We propose a planar junctionless transistor (JLT) in silicon-on-insulator (SOI) with non-uniform channel doping in vertical direction to improve the ON to OFF drain current ratio. In single gate JLT in SOI, a thin device layer is depleted in the off-state from the top of the layer and the leakage current flows through bottom of the device layer, and the leakage current depends on the device layer thickness. We show that the decrease of doping in vertical direction suppresses the leakage current flowing through the bottom of the device by decreasing conductivity at the bottom of the device layer.

Monte Carlo simulation study of spin transport in single layer graphene

Spin transport in single layer graphene is studied in this work using a semiclassical Monte Carlo simulation, and a comparison is made to bi-layer graphene. Spin relaxation is modeled using the D’yakonov-Perel and Elliot-Yafet mechanisms. It is shown that bi-layer graphene has a higher spin relaxation length compared to single layer graphene, and this has also been observed experimentally. An explanation of this difference is given in terms of the band structures of the two materials.

Analog performance of Si junctionless tunnel field effect transistor and its improvisation using III–V semiconductor

In this paper, the analog performance of a Si double gate Junctionless Tunnel Field Effect Transistor (DG-JLTFET) has been studied and improvised using a ternary III–V semiconductor compound, indium aluminium arsenide. The analog performance parameters are extracted using device simulations and also compared with the Si JLTFET. We show that III–V JLTFET delivers much better performance parameters, in comparison to Si JLTFET, which includes transconductance generation efficiency (Gm/ID), intrinsic gain (GmRo) and unity gain frequency (fT) along with various gate capacitances.

Monte Carlo study of Germanium n- and pMOSFETs

In this paper, we perform fullband Monte Carlo simulations of Ge bulk nand pMOSFETs and compare them with their Si counterparts. We consider transport in the presence of phonon, ionized impurity, surface roughness scattering, and impact ionization. Quantum confinement in the inversion layer is taken into account in the form of a modified potential. Germanium devices gave higher drive current when compared with Si devices for the device structures studied. Consistent with the arguments of Lundstrom, the performance enhancement of Ge MOSFETs lies between that which would be expected based on the higher mobility alone, and the much smaller advantage, if any, offered in the ballistic limit where transport is governed by thermal injection velocities from the source.

Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime

We propose a hetero-gate-dielectric double gate junctionless transistor (HGJLT), taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects of band-to-band tunnelling (BTBT) in the sub-threshold region. A junctionless transistor (JLT) is turned off by the depletion of carriers in the highly doped thin channel (device layer) which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel. These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor (n–p–n BJT for channel JLT) in the lateral direction by the source (emitter), channel (base) and drain (collector) regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.

Spin transport in bilayer graphene

In this work, we perform a study of spin transport in bilayer graphene using semiclassical Monte Carlo simulation. Both the D’yakonov–Perel’ (DP) and Elliot–Yafet (EY) mechanisms for spin relaxation are considered. A vertical field of varying magnitude is applied across the bilayer and the dependence of the spin relaxation length on the applied field is considered. It is found that the spin relaxation length is a function of the applied vertical field, due to the effects of the EY and DP mechanisms, and the relaxation length reaches a maximum for a particular value of the vertical field.

Analog performance of double gate junctionless tunnel field effect transistor

For the first time, we investigate the analog performance of n-type double gate junctionless tunnel field effect transistor (DG-JLTFET) and the results are compared with the conventional n-type double gate tunnel field effect transistor (DG-TFET) counterpart. Using extensive device simulations, the two devices are compared with the following analog performance parameters, namely transconductance, output conductance, output resistance, intrinsic gain, total gate capacitance and unity gain frequency. From the device simulation results, DG-JLTFET is found to have significantly better analog performance as compared to DG-TFET.

Ripple carry adder using five input majority gates

Quantum dot Cellular Automata (QCA) is a transistor less computational model which is expected to provide high density nanotechnology implementations of various CMOS circuits. QCA has been constrained by the number of basic gates available. This paper aims at using five input majority gate to implement two adder circuits achieving implementation in lesser number of cells and higher density.

High-k double gate junctionless tunnel FET with a tunable bandgap

In the present work, the performance of a heterostructure double gate junctionless tunnel FET (HJL-DGTFET) having a tunable source bandgap has been analyzed using a 2D simulation technique. The tunable source HJL-DGTFET shows a high ON-current (≈ 6.5 × 10−5 A μm−1) and a very low OFF-current (≈ 4.8 × 10−17 A μm−1). The device shows a point subthreshold slope ≈ 36.2 to 26.8 mV per decade and the average subthreshold slope ≈ 86.1 to 84.2 mV per decade for 0.0–40.0% Ge-mole fractions at room temperature with an ION/IOFF ratio of 1012. The excellent switching characteristics and steeper subthreshold slope at room temperature indicate that this is a promising candidate for the replacement of bulk MOSFETs. In this article, the optimization of device parameters such as the oxide thickness (tox), gate dielectric material and spacer has also been discussed in detail.