Alaa Hussein

Fractional-N frequency synthesizer for wireless communications

With the advancement of radio frequency (RF) technology and requirement for more integration, new RF wireless architectures are needed. One of the most critical components in a wireless transceiver is the frequency synthesizer. It largely affects all three dimensions of a wireless transceiver design: cost, battery lifetime, and performance. The common approach to frequency synthesis design for wireless communication is to design an analog-compensated fractional-N phaselocked loop (PLL). However, this technique lacks adequate fractional spur suppression for third generation wireless standards. In this paper, a new sigma-delta PLL architecture is reported to enhance the above mentioned limitation with the aid of modified digital sigma-delta modulator to completely randomize fractional spurs present in fractional-N PLLs using feedback signal which serves as a dithering signal. This aids in fully integrating a high-performance PLL frequency synthesizer, and hence reducing cost. The use of this architecture is examined to give as much as 14 dBs reduction in the fractional spurs.

A novel current-mode ultra low power analog CMOS four quadrant multiplier

A novel CMOS current mode analog multiplier is presented. The design is based on using MOSFET operating in subthreshold region to achieve ultra low power dissipation. The circuit is operated from ± 0.75V DC supply. The proposed circuit has been simulated using Tanner in 0.35μm TSMC CMOS process. Simulation results show that the total power dissipation is 2.3μW, total harmonic distortion is 0.7%, maximum linearity error is 0.3% and the bandwidth is 2.8MHz.

Dual-mode bluetooth/wireless local area network channel-select filter for direct conversion receivers

System level analysis is used to extract various specifications of the channel select filter for integrated dual-mode CMOS bluetooth (BT)/wireless local area network (WLAN; IEEE 802.11b) receivers. A digitally programmable active-RC filter suitable for direct conversion topology is presented. Six-bit R-2R ladders are used to adjust the filter bandwidth with tuning resolution better than 1.56%. Experimental results obtained from 0.35 µm CMOS chips show that using a fourth-order filter satisfies the selectivity requirements of both applications. The filter exhibits spurious free dynamic range of 70.6 and 61.2 dB for BT and WLAN, respectively.

VSC-HVDC system stability augmentation with bridge type fault current limiter

Voltage source converter high voltage DC (VSC-HVDC) system has number of advantages over traditional line commutated converter HVDC (LCC-HVDC). However, VSC-HVDC system is exposed to high current due to faults having great negative effect on converters. In order to limit fault current to relatively low level, bridge type fault current limiter (BFCL) for VSC-HVDC system has been proposed in this study. Fault current limiters are placed with the AC gird sides of VSC-HVDC system. Real and reactive power controller for the VSC-HVDC has been developed based on current control mode. Symmetrical as well as unsymmetrical faults are applied to evaluate the effectiveness of proposed BFCL controller in order to limit the fault current and improve system stability. Simulations are carried out with real time digital simulator (RTDS) to validate the efficacy of the proposed BFCL solution. The results show the potential of the proposed scheme to limit the fault current and improve greatly the system performance.

A New Capacitor-Less Buck DC-DC Converter for LED Applications

In this paper, a new capacitor-less DC-DC converter is proposed to be used as a light emitting diode (LED) driver. The design is based on the utilization of the internal capacitance of the LED to replace the smoothing capacitor. LED lighting systems usually have many LEDs for better illumination that can reach multiple tens of LEDs. Such configuration can be utilized to enlarge the total internal capacitance and hence minimize the output ripple. Also, the switching frequency is selected such that a minimum ripple appears at the output. The functionality of the proposed design is confirmed experimentally and the efficiency of the driver is 85% at full load.

A CMOS channel select filter for dual mode Bluetooth/WLAN direct-conversion receiver

Design of a CMOS 4th-order channel select filter for integrated dual mode Bluetooth/WLAN direct-conversion receiver is presented. The bandwidth of the filter can be programmed from 200 kHz to 8 MHz to accommodate both standards. The proposed filter provides low power, and small area design solution. Simulation results show that the filter satisfies the selectivity and dynamic range requirements of both applications while consuming total standby power of 5.7 mW.

A novel fuzzy logic controller for smart load voltage regulation

Electric spring (ES) is a novel smart grid technology, which is based on power electronic components. It has multitude of benefits associated with its widespread use at distribution level, which includes voltage profile enhancement, power imbalance mitigation, and power quality improvement. With the ever increasing need of incorporating intermittent renewable energy sources (RES), electric spring offers a viable solution to the problems linked with such energy sources. A new generation of electrical loads is also recently proposed, known as smart loads, which is the outcome of integrating electric spring in series with a non-critical load. This work proposes a novel control scheme for electric spring based on fuzzy logic to regulate mains voltage. Simulations are carried out for ES based on conventional PI controller, fuzzy logic controller, and adaptive fuzzy PI and their results are analytically compared.

A new capacitor-less LED drive

In this paper a new capacitor-less LED drive is proposed. The design is based on the utilization of the internal capacitance of the LED to replace the smoothing capacitor. LED lighting systems usually have many LEDs for better illumination that can reach multiple tens of LEDs. Such configuration can be utilized to enlarge the total internal capacitance and hence minimize the output ripple. In addition, the switching frequency is selected such that minimum ripple appears at the output. The functionality of the proposed design is confirmed experimentally and the efficiency of the drive is 85% at full load.

Improved High Speed, Low Power CMOS Multiplier

A high speed four quadrant current mode multiplier is presented. It is based on CMOS devices arranged in dual trans-linear loops and working in saturation region. The designed circuit operates under the voltage supply of ±1.5V. Design simulation was carried out using Tanner EDA Tools v13.0 with level 49 parameters (BSIM3 v3.1) in 0.35µm standard CMOS technology. Simulation results show that the multiplier has a 3dB bandwidth of 440MHz, linearity error of 1.1% and maximum power consumption of 158µW. The analog multiplier is used to carry out amplitude modulation whose results are also reported.

A low voltage and low power current-mode field programmable analog computational unit

A new current-mode analog computational unit (ACU) is presented. The ACU can be digitally programmed to produce multiplying, squaring and inverse functions. The design is based on using MOSFETs operating in subthreshold region to achieve ultra-low power dissipation. The circuit is operated from a ± 0.75V DC supply. The proposed circuit has been simulated using Tanner in 0.35μm TSMC CMOS process. Simulation results confirm the functionality of the circuit. The total power consumption is 2.3μW, total harmonic distortion is 1.1%, maximum nonlinearity error is 0.3% and the bandwidth is 2.3MHz.