Hussain A. Alzaher

A CMOS highly linear channel-select filter for 3G multistandard integrated wireless receivers

A new approach for designing digitally programmable CMOS integrated baseband filters is presented. The proposed technique provides a systematic method for designing filters exhibiting high linearity and low power. A sixth-order Butterworth low-pass filter with 14-bit bandwidth tuning range is designed for implementing the baseband channel-select filter in an integrated multistandard wireless receiver. The filter consumes a current of 2.25 mA from a 2.7-V supply and occupies an area of 1.25 mm/sup 2/ in a 0.5-/spl mu/m chip. The proposed filter design achieves high spurious free dynamic ranges (SFDRs) of 92 dB for PDC (IS-54), 89 dB for GSM, 84 dB for IS-95, and 80 dB for WCDMA.

A CMOS fully balanced differential difference amplifier and its applications

We present the fully balanced version of the differential difference amplifier (DDA) as an essential building block for implementing fully differential architectures of analog CMOS integrated circuits (ICs). It is demonstrated that the fully balanced differential difference amplifier (FBDDA) provides the solution for systematically developing fully differential versions of any single-ended op-amp based circuit. It is also shown that, unlike the DDA, the FBDDA exhibits a wide input range without demanding complex circuitry. A low-power class AB CMOS realization of the proposed circuit has been designed and fabricated in a 1.2 /spl mu/m technology. All proposed design techniques and circuits were experimentally verified.

A CMOS fully balanced second-generation current conveyor

The design and implementation of a high performance CMOS fully balanced second-generation current conveyor (FBCCII) is presented. The proposed circuit is essential to extend the use of the CCII based circuits to integrated circuits (ICs) applications. The circuit is developed by applying the current sensing technique to a fully balanced version of a differential difference amplifier (DDA). A low power class AB circuit realization is implemented in a 1.2-/spl mu/m CMOS technology and its different characteristics are measured. Design examples of realizing fully balanced variable gain amplifiers (VGAs) and a bandpass filter based on the proposed FBCCII are given. Experimental results of the proposed circuits are included.

New Universal Filter with One Input and Five Outputs Using Current-Feedback Amplifiers

A new universal voltage-mode second-order filter circuit is presented. The circuit uses five current-feedback operational amplifiers, two grounded capacitors three grounded resistors and three floating resistors. The circuit can realize all the standard filter functions; lowpass, highpass, bandpass, notch and allpass, without changing the passive elements. The proposed circuit enjoys independent grounded-resistance-control of the natural frequency and the bandwidth, low output impedances, high input impedance as well as low active and passive sensitivities.

A CMOS fully balanced four-terminal floating nullor

This paper presents design and implementation of a CMOS fully balanced realization of the four-terminal floating nullor (FTFN). The proposed fully balanced FTFN (FBFTFN) is an essential building block for implementing fully balanced architectures of both voltage and current-mode analog CMOS integrated circuits (ICs). A low-power class AB CMOS realization of the proposed circuit is fabricated in a 1.2-/spl mu/m technology. The proposed circuit has numerous applications. Several applications including fully balanced amplifiers, filters, and sinusoidal oscillators are presented. All proposed design techniques and circuits are experimentally verified.

A CMOS Digitally Programmable Universal Current-Mode Filter

A new digitally programmable universal current-mode biquad filter is proposed. The filter is based on digitally controlled current followers (DCCFs). It utilizes gains of the DCCFs to provide precise frequency and/or gain characteristics that can be digitally tuned over a wide range. All parameters of the proposed filter can be adjusted independently. Experimental results obtained from a 0.35-mum standard CMOS chip are provided.

A complementary metal–oxide semiconductor digitally programmable current conveyor

SUMMARY A second-generation current conveyor with digitally programmable current gains is presented. A current division network with zero standby power consumption is utilized in two different ways to provide both gain and attenuation of the second-generation current conveyors current transfer characteristics. The proposed topology overcomes several drawbacks of the previous solutions through affording a more power and area efficient solution while exhibiting relatively wider tuning range and bandwidth. A variable-gain amplifier and a two-integrator-loop filter biquad providing low-pass and band-pass responses are given as application examples. A modified two-integrator-loop topology is developed to offer independent control of the pole frequency and quality factor without disturbing the passband gain. Simulation results obtained from a standard 0.18 µm complementary metal–oxide semiconductor process are given. Copyright

A new generation of global wireless compatibility

The expanding growth of wireless communications has led to the proliferation of different standards. The highly competitive market demands low-cost, low-power, and small form-factor devices. This calls for the development of a single-chip, third-generation (3G) receiver capable of adapting to the various communications standards in a low-cost CMOS technology. However, fully integrated receiver architectures require the elimination of discrete high-Q image rejection and IF filters. Thus, the received signal is down-converted to baseband without channel filtering, which most frequently results in the presence of strong adjacent channel blockers along with the desired signal. Therefore, it is required from the baseband filter design to exhibit a high-dynamic range, a programmable bandwidth to accommodate different standards, precise tuning to select the desired channel within a standard, low power, and a small chip area. This article discusses the 3G wireless systems with a focus on the design of a reconfigurable baseband chain that precedes the ADC of a multistandard fully integrated wireless receiver. The baseband chain is adapted to accommodate the GSM, IS-95, and wideband CDMA wireless standards.

A Highly Linear Fully Integrated Powerline Filter for Biopotential Acquisition Systems

Powerline interference is one of the most dominant problems in detection and processing of biopotential signals. This work presents a new fully integrated notch filter exhibiting high linearity and low power consumption. High filter linearity is preserved utilizing active-RC approach while IC implementation is achieved through replacing passive resistors by R-2R ladders achieving area saving of approximately 120 times. The filter design is optimized for low power operation using an efficient circuit topology and an ultra-low power operational amplifier. Fully differential implementation of the proposed filter shows notch depth of 43 dB (78 dB for 4th-order) with THD of better than -70 dB while consuming about 150 nW from 1.5 V supply.

Optimal Low Power Complex Filters

Realizations of voltage-mode and current-mode complex filters based on transconductance, transresistance, and current amplifiers for intermediate frequency (IF) applications are systematically developed. Various amplifiers are realized utilizing the second generation current conveyor (CCII) to promote comparisons at device levels. The adopted approach shows that the most efficient designs in terms of the number of active components are current-mode filters based on the transconductance and current amplifiers. As an application example, a 4th-order complex filter based on the CA is designed for low-IF Bluetooth receiver. Fabricated in a standard 0.18 μm CMOS technology, experimental results show that the proposed design offers improved characteristics over the available solutions in terms of power consumption and spurious-free dynamic range (SFDR). The filter exhibits in-band SFDR of 65.8 dB while consuming 1 mW.