Alain Artieri

Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors.

Models for cache yield and coverage for radiation-induced soft errors quantify the trade-off between the minimum supply voltage (VMIN) and the soft-error protection when applying error-correcting codes (ECC) to a cache. Model predictions of the VMIN benefit and soft-error coverage agree closely with silicon measurements from a 7Mb data cache in a 20nm test chip when considering either single-error correction, double-error detection (SECDED) or double-error correction, triple-error detection (DECTED) codes. Silicon measurements demonstrate a VMIN reduction of 19% and 27% from SECDED and DECTED, respectively, as compared to a cache without ECC. Moreover, silicon measurements highlight a salient insight in that only 0.12% of the cache words contain an error when operating at the cache VMIN with SECDED. Thus, SECDED simultaneously enables a 19% lower VMIN and 99.88% coverage for radiation-induced soft errors. Model projections indicate larger benefits in VMIN and soft-error protection as future cache sizes increase.

Trading-off on-die observability for cache minimum supply voltage reduction in system-on-chip (SoC) processors

Circuit techniques for reducing the minimum supply voltage (V MIN ) of last-level and intermediate static random-access memory (SRAM) caches enhance processor energy efficiency. For the first time at a 16nm technology node, projections of a high-density 6-transistor SRAM bit cell indicate that the VMIN of a 4Mb or larger cache exceeds the maximum supply voltage (V MAX ) for reliability. Thus, circuit techniques for cache VMIN reduction are transitioning from an energy-efficient solution to a requirement for cache functionality. Traditionally, error-correcting codes (ECC) such as single-error correction, double-error detection (SECDED) aim to protect the cache operation from radiation-induced soft errors. Moreover, during the qualification of a system-on-chip (SoC) processor, test engineers monitor the rate of correctable cache errors from SECDED for observing the on-die interactions between integrated components (e.g., CPU, GPU, DSP, etc.). This presentation highlights the opportunity to exploit ECC for reducing the cache V MIN while simultaneously providing coverage for radiation-induced soft errors. Silicon test-chip measurements from a 7Mb data cache in a 20nm technology demonstrate a V MIN reduction of 19% from SECDED. In addition, silicon measurements provide a salient insight in that only 0.12% of the cache words contain an error when operating at the cache V MIN with SECDED. Therefore, SECDED improves V MIN by 19% while maintaining 99.88% coverage for radiation-induced soft errors. In applying SECDED for a lower cache VMIN, the rate of correctable errors exponentially increases, thus eliminating a useful metric for on-die observability. The presentation concludes by offering alternative solutions for on-die observability.