Francois Ibrahim Atallah

8.5 A 16nm auto-calibrating dynamically adaptive clock distribution for maximizing supply-voltage-droop tolerance across a wide operating range

System-on-chip (SoC) processor cores experience high-frequency supply voltage (VDD) droops when the current in the power delivery network abruptly changes in response to workload variations, thus degrading performance and energy efficiency. Previous adaptive circuit techniques aim to reduce the effects of VDD droops by sensing the VDD variation with an on-die monitor and adjusting the clock frequency (FCLK) [1-2] or by directly modulating the phase-locked loop (PLL) clock output with changes in the core VDD to implicitly adapt FCLK [3]. The adaptive response time and complex analog circuits limit the benefits of these techniques for a wide range of FCLK and VDD operating conditions. The adaptive clock distribution (ACD) [4-5] exploits the path clock-data delay compensation during a VDD droop to enable a sufficient response time to proactively adapt FCLK. Although the ACD mitigates the impact of VDD droops on performance and energy efficiency, the previous designs require extensive post-silicon tester calibration of the dynamic variation monitor (DVM) to accurately detect the onset of the VDD droop. Since SoC cores operate across a wide range of FCLK, VDD, temperature, and process conditions, the DVM requires a unique calibration for each operating point, thus resulting in prohibitively expensive test time for high-volume products. This paper describes an ACD design in a 16nm [6] test chip with an auto-calibration circuit to enable in-field, low-latency tuning of the DVM across a wide range of operating conditions to maximize the ACD benefits, while eliminating the costly overhead from tester calibration.

A 16 nm All-Digital Auto-Calibrating Adaptive Clock Distribution for Supply Voltage Droop Tolerance Across a Wide Operating Range

A 16 nm all-digital auto-calibrating adaptive clock distribution (ACD) enhances processor core performance and energy efficiency by mitigating the adverse effects of high-frequency supply voltage (VDD) droops. The ACD integrates a tunable-length delay prior to the global clock distribution to prolong the clock-data delay compensation in core paths for multiple cycles after a droop occurs to provide a sufficient response time for clock frequency (FCLK) adaptation. A dynamic variation monitor (DVM) detects the onset of the droop and interfaces with an adaptive control unit and clock divider to reduce FCLK in half at the TLD output to avoid path timing-margin failures. An auto-calibration circuit enables in-field, low-latency tuning of the DVM to accurately detect VDD droops across a wide range of operating conditions. The auto-calibration circuit maximizes the VDD-droop tolerance of the ACD while eliminating the overhead from tester calibration. From 109 die measurements across a wafer, the auto-calibrating ACD recovers a minimum of 90% of the throughput loss due to a 10% VDD droop in a conventional design for 100% of the dies. ACD measurements demonstrate simultaneous throughput gains and energy reductions ranging from 13% and 5% at 0.9 V to 30% and 13% at 0.6 V, respectively.

Adaptive power gating of 32-bit Kogge Stone adder

Static power consumes a significant portion of the available power budget. Consequently, leakage current reduction techniques such as power gating have become necessary. Standard global power gating approaches are an effective method to reduce idle leakage current, however, global power gating does not consider partially idle circuits and imposes significant delay and routing constraints. An adaptive power gating technique is applied locally to a 32-bit Kogge Stone adder, and evaluated at the 16nm FinFET technology node. This high granularity adaptive power gating approach employs a local controller to lower energy use and reduce circuit overhead. The controller conserves additional power when the circuit is partially idle (based on the inputs to the adder) by adaptively powering down inactive blocks. Moreover, the local controller reduces routing complexity since a global power gating signal is not required. The proposed adaptive power gating technique exhibits significant energy savings, ranging from 8% to 21%. This technique targets partially idle circuits, and therefore complements rather than replaces global power gating techniques. A 12% delay overhead results in a 5% area overhead. This delay overhead is reduced to 5% by increasing the area overhead to 16%, and can be further reduced by trading off additional area. HighlightsAn adaptive power gating technique is applied locally to a 32-bit Kogge Stone adder, and evaluated at the 16nm FinFET technology node.Local controller conserves additional power when the circuit is partially idle (based on the inputs to the adder) by adaptively powering down inactive blocks.Significant energy savings, ranging from 8% to 21%, are enabled by this adaptive power gating methodology.This technique targets partially idle circuits, and therefore complements rather than replaces global power gating techniques.

Exploiting error-correcting codes for cache minimum supply voltage reduction while maintaining coverage for radiation-induced soft errors.

Models for cache yield and coverage for radiation-induced soft errors quantify the trade-off between the minimum supply voltage (VMIN) and the soft-error protection when applying error-correcting codes (ECC) to a cache. Model predictions of the VMIN benefit and soft-error coverage agree closely with silicon measurements from a 7Mb data cache in a 20nm test chip when considering either single-error correction, double-error detection (SECDED) or double-error correction, triple-error detection (DECTED) codes. Silicon measurements demonstrate a VMIN reduction of 19% and 27% from SECDED and DECTED, respectively, as compared to a cache without ECC. Moreover, silicon measurements highlight a salient insight in that only 0.12% of the cache words contain an error when operating at the cache VMIN with SECDED. Thus, SECDED simultaneously enables a 19% lower VMIN and 99.88% coverage for radiation-induced soft errors. Model projections indicate larger benefits in VMIN and soft-error protection as future cache sizes increase.

Digitally-assisted leakage current supply circuit for reducing the analog LDO minimum dropout voltage

A digitally-assisted leakage current supply (LCS) circuit reduces the maximum current demand for analog low-dropout (LDO) voltage regulators to lower the minimum dropout voltage (VDO. MIN), and consequently, enable a wider range of LDO operation for power savings in system-on-chip processor cores. From silicon measurements in a 130nm test chip, the LCS assisted hybrid LDO decreases VDO, MIN by 30–38%, resulting in core power reduction of 21–28% at equal clock frequencies within the wider LDO operating range.

A 16nm configurable pass-gate bit-cell register file for quantifying the V MIN advantage of PFET versus NFET pass-gate bit cells

A 16nm configurable pass-gate bit-cell register file allows a direct comparison of NFET versus PFET pass-gate bit cells for early technology evaluation. The configurable pass gate enables either a transmission-gate (TG), an NFET pass gate, or a PFET pass gate. From silicon test-chip measurement, the register file with PFET pass-gate bit cells achieves a 33% minimum supply voltage (VMIN) reduction in a 16nm FinFET technology and a 40% VMIN reduction in an enhanced 16nm FinFET technology as compared to a register file with NFET pass-gate bit cells. Test-chip measurements highlight the superior benefits of the PFET drive current relative to the NFET drive current at low voltages. The VMIN improvement with a PFET pass-gate bit cell represents a paradigm-shift from traditional CMOS circuit-design practices.

Trading-off on-die observability for cache minimum supply voltage reduction in system-on-chip (SoC) processors

Circuit techniques for reducing the minimum supply voltage (V MIN ) of last-level and intermediate static random-access memory (SRAM) caches enhance processor energy efficiency. For the first time at a 16nm technology node, projections of a high-density 6-transistor SRAM bit cell indicate that the VMIN of a 4Mb or larger cache exceeds the maximum supply voltage (V MAX ) for reliability. Thus, circuit techniques for cache VMIN reduction are transitioning from an energy-efficient solution to a requirement for cache functionality. Traditionally, error-correcting codes (ECC) such as single-error correction, double-error detection (SECDED) aim to protect the cache operation from radiation-induced soft errors. Moreover, during the qualification of a system-on-chip (SoC) processor, test engineers monitor the rate of correctable cache errors from SECDED for observing the on-die interactions between integrated components (e.g., CPU, GPU, DSP, etc.). This presentation highlights the opportunity to exploit ECC for reducing the cache V MIN while simultaneously providing coverage for radiation-induced soft errors. Silicon test-chip measurements from a 7Mb data cache in a 20nm technology demonstrate a V MIN reduction of 19% from SECDED. In addition, silicon measurements provide a salient insight in that only 0.12% of the cache words contain an error when operating at the cache V MIN with SECDED. Therefore, SECDED improves V MIN by 19% while maintaining 99.88% coverage for radiation-induced soft errors. In applying SECDED for a lower cache VMIN, the rate of correctable errors exponentially increases, thus eliminating a useful metric for on-die observability. The presentation concludes by offering alternative solutions for on-die observability.