Alain C. Diebold

Handbook of Silicon Semiconductor Metrology

Introduction - silicon semiconductor metrology. Part 1 Transistor fabrication metrology: gate dielectric metrology metrology for ion implantation MOS device characterization carrier illumination characterization of ultra-shallow implants modelling of statistical manufacturing sensitivity and of process control and metrology requirements for a 0.18Mum NMOSFET. Part 2 On-chip interconnect metrology: overview of metrology for on-chip interconnect metrology for on-chip interconnectdielectrics thin film metrology using impulsive stimulated thermal scattering (ISTS) metal interconnect process control using picosecond ultrasonics sheet resistance measurements of interconnect films characterization of low dielectric constantmaterials high resolution profilometry for CMP and etch metrology. Part 3 Lithography metrology: critical dimension metrology in the scanning electron microscope scanned probe microscope dimensional metrology electrical DC metrology and relatedreference materials metrology of image placement scatterometry for semiconductor metrology. Part 4 Defect detection and characterization: unpatterned wafer defect detection particle and defect characterization calibration of particle detectionsystems. Part 5 Sensor based metrology: in-situ metrology. Part 6 Data management: metrology data management and information systems. Part 7 Electrical measurement based statistical metrology: statistical metrology. Part 8 Overviews of key measurement andcalibration technology: physics of optical metrology of silicon based semiconductor devices UV, VUV and extreme UV spectroscopic reflectometry and ellipsometry analysis of thin layer structures by x-ray reflectometry ion beam methods electronmicroscopy based measurement of feature thickness and calibration of reference materials status of lithography at the end of 2000.

Optical properties of large-area polycrystalline chemical vapor deposited graphene by spectroscopic ellipsometry

Spectroscopic ellipsometry was used to characterize the complex refractive index of chemical vapor deposition (CVD) graphene grown on copper foils and transferred to glass substrates. Two ellipsometers, with respective wavelength ranges extending into the ultraviolet and infrared (IR), have been used to characterize the CVD graphene optical functions. The optical absorption follows the same relation to the fine structure constant previously observed in the IR region, and displays the exciton-dominated absorption peak at ∼4.5 eV. The optical functions of CVD graphene show some differences when compared to published values for exfoliated graphene.

Spatial distributions of trapping centers in HfO2∕SiO2 gate stacks

A methodology to analyze charge pumping (CP) data, which allows positions of probing traps in the dielectric to be identified, was applied to extract the spatial profile of traps in SiO2∕HfO2 gate stacks. The results suggest that traps accessible by CP measurements in a wide frequency range, down to few kilohertz, are located within or near the interfacial SiO2 layer rather than in the bulk of the high-k film.

Complete band offset characterization of the HfO2/SiO2/Si stack using charge corrected x-ray photoelectron spectroscopy

The HfO2–Si valence and conduction band offsets (VBO and CBO, respectively) of technologically relevant HfO2/SiO2/Si film stacks have been measured by several methods, with several groups reporting values within a range of ∼1 eV for both quantities. In this study we have used a combination of x-ray photoemission spectroscopy (XPS) and spectroscopic ellipsometry to measure the HfO2–Si VBO and CBO of both as-deposited and annealed stacks. Unlike previous XPS based measurements of the HfO2–Si VBO, we have corrected for the effect of charging in the XPS measurement. We find that after correction for charging, the HfO2–Si VBOs are decreased from their typical XPS-measured values, and agree better with values measured by UV photoemission spectroscopy and internal photoemission. We also report values for the rarely reported HfO2–SiO2 and SiO2–Si VBOs and CBOs in HfO2/SiO2/Si stacks. In addition to the band offsets, XPS was used to measure the band bending in the Si substrate of HfO2/SiO2/Si film stacks. Unanneal...

Spectroscopic ellipsometry characterization of HfxSiyOz films using the Cody–Lorentz parameterized model

A parameterized, Kramers–Kronig consistent, Cody–Lorentz optical model is used to simulate the dielectric response of thin HfxSiyOz films. Optical constants are determined in the range 0.75–8.35eV. The Cody–Lorentz model has three specific differences when compared to the previously employed Tauc–Lorentz model: (1) weak exponential absorption below the band gap, (2) a modified joint density-of-states, and (3) a restriction on the e1(∞) parameter. These three differences allow the Cody–Lorentz model to have an improved fit to experimental data. As a result of a more accurate optical model for HfxSiyOz, we were able to identify an interfacial layer with thickness in close agreement with transmission electron microscopy measurements. Use of the Tauc–Lorentz model when fitting the same experimental data could not identify an interfacial layer. Results are also discussed in which the Cody–Lorentz model shows sensitivity to varying degrees of silicate composition.

Characterization of two‐dimensional dopant profiles: Status and review

The National Technology Roadmap for Semiconductors calls for development of two‐ and three‐dimensional dopant profiling methods for calibration of technology computer‐aided design process simulators. We have previously reviewed 2D dopant profiling methods. In this article, we briefly review methods used to characterize etched transistor cross sections by expanding our previous discussion of scanned probe microscopy methods. We also mention the need to participate in our ongoing comparison of analysis results for test structures that we have provided the community.

Semiconductor Characterization: Present Status and Future Needs

Contents: 1. Drivers for Silicon Process Development and Manufacturing. 2. Metrology Requirements for Beyond 0.35-um Geometries 3. Silicon Wafers, Gate Dielectrics, and Process Simulation. 4. Interconnects and Failure Analysis. 5. Critical Analytical Methods. 6. In-Situ, Real Time Diagnosis, Analysis, and Control. 7. Frontiers in Compound Semiconductors.

Randomly oriented Angstrom‐scale microroughness at the Si(100)/SiO2 interface probed by optical second harmonic generation

Femtosecond pulses from a Kerr–Lens mode‐locked Ti:sapphire laser are used to generate second harmonic from a series of native‐oxidized Si(100)/SiO2 and hydrogen‐terminated Si(100) samples prepared with systematically varied interfacial microroughness with root‐mean‐square feature heights ranging from 0.6 to 4.3 A. Rotationally anisotropic second harmonic signals using different polarization configurations were measured in air and correlated with atomic force microscopy measurements. The results demonstrate rapid, noncontact, noninvasive measurement of Angstrom‐level Si(100)/SiO2 interface roughness by optical second harmonic generation.

Spatial Distributions of Trapping Centers in

An analysis methodology for charge pumping (CP) measurements was developed and applied to extract spatial distributions of traps in SiO 2/HfO2 gate stacks. This analysis indicates that the traps accessible by CP measurements in the frequency range down to a few kilohertz are located primarily within the SiO2 layer and HfO2/SiO2 interface region. The trap density in the SiO2 layer increases closer to the high-kappa dielectric, while the trap spatial profile as a function of the distance from the high-kappa film was found to be dependent on high-kappa film characteristics. These results point to interactions with the high-kappa dielectric as a cause of trap generation in the interfacial SiO2 layer

\hbox{HfO}_{2}/\hbox{SiO}_{2}

Abstract The thickness of silicon dioxide that is used as the transistor gate dielectric in most advanced memory and logic applications has decreased below 7 nm. Unfortunately, the accuracy and reproducibility of metrology used to measure gate dielectric thickness during manufacture of integrated circuits remains in some dispute. In addition, detailed materials characterization studies have resulted in a variety of descriptions for the oxide-interface–substrate system. Part of the problem is that each method measures a different quantity. Another related issue concerns how one should define and model the critical dielectric/substrate interface. As scaling continues, the interface between silicon dioxide and silicon becomes a larger part of the total thickness of the oxide film. Although materials characterization studies have focused on this interface, there have been few attempts to compare the results of these methods based on an understanding of the models used to interpret the data. In this review, we describe the physical and electrical characterization of the interfacial layer. Infrared absorption data are reviewed and previous interpretations of the LO/TO phonon shifts as a function of oxide thickness are refined. We correlate the available results between physical methods and between physical and electrical methods. This information is essential to inclusion of an interfacial layer in optical models used to measure silicon dioxide inside the clean room. We also describe some characterization issues for nitrided oxides.