P. Y. Hung

Chloride molecular doping technique on 2D materials: WS2 and MoS2.

Low-resistivity metal-semiconductor (M-S) contact is one of the urgent challenges in the research of 2D transition metal dichalcogenides (TMDs). Here, we report a chloride molecular doping technique which greatly reduces the contact resistance (Rc) in the few-layer WS2 and MoS2. After doping, the Rc of WS2 and MoS2 have been decreased to 0.7 kΩ·μm and 0.5 kΩ·μm, respectively. The significant reduction of the Rc is attributed to the achieved high electron-doping density, thus a significant reduction of Schottky barrier width. As a proof-of-concept, high-performance few-layer WS2 field-effect transistors (FETs) are demonstrated, exhibiting a high drain current of 380 μA/μm, an on/off ratio of 4 × 10(6), and a peak field-effect mobility of 60 cm(2)/(V·s). This doping technique provides a highly viable route to diminish the Rc in TMDs, paving the way for high-performance 2D nanoelectronic devices.

300mm FinFET results utilizing conformal, damage free, ultra shallow junctions (X j ∼5nm) formed with molecular monolayer doping technique

We demonstrate for the first time, a 20nm FinFET using a new, conformal, and damage-free monolayer doping technique. Unlike conventional ion-implantation, this approach makes use of a dopant-containing precursor to uniformly assemble a monolayer of covalently bonded dopants to enable an ultra-shallow (Xj∼5nm) and abrupt (0.6nm/dec) junction formation around a high aspect ratio fin structure, which overcomes the possible FinFET pitch scaling limitations of traditional doping techniques. FinFETs featuring MLD junctions were successfully demonstrated with good electrostatics control down to a gate length of ∼40nm. With further scaling of the fin width, sub-threshold swing and threshold voltage roll-off can be further improved. This low damage and conformal doping is a promising technique to address key FinFET scaling issues associated with parasitic series resistance and short channel control for the 15nm node and beyond.

Effective Modulation of Ni Silicide Schottky Barrier Height Using Chlorine Ion Implantation and Segregation

Using a presilicide implantation approach, we demonstrate that the Schottky barrier height (SBH) of NiSi/n-Si(100) can be modulated by doping a Si substrate with a halogen species such as chlorine. Activation energy measurements indicate that an ultralow barrier of 0.08 eV for NiS/n-Si can be achieved when a high dose (~1 times 1015 cm2) of chlorine is implanted prior to Ni silicidation. A secondary ion mass spectroscopy analysis on the presilicide Cl-implanted NiSi shows chlorine segregates at the interface with SBH tuning from 0.68 to 0.08 eV on n-Si and a corresponding increase in hole SBH on p-Si(100). The presilicide Cl-implanted NiSi film also demonstrates an enhanced thermal stability with a low sheet resistively of < 28 muOmega even up to 850degC.

High-performance MoS 2 field-effect transistors enabled by chloride doping: Record low contact resistance (0.5 kΩ·µm) and record high drain current (460 µA/µm)

In this paper, we report a novel chemical doping technique to reduce the contact resistance (R_c) of transition metal dichalcogenides (TMDs) - eliminating two major roadblocks (namely, doping and high R_c) towards demonstration of high-performance TMDs field-effect transistors (FETs). By using 1,2 dichloroethane (DCE) as the doping reagent, we demonstrate an active n-type doping density > 2×10¹⁹ cm^-3 in a few-layer MoS₂ film. This enabled us to reduce the R_c value to a record low number of 0.5 kΩ·μm, which is ~10×lower than the control sample without doping. The corresponding specific contact resistivity (ρ_c) is found to decrease by two orders of magnitude. With such low R_c, we demonstrate 100 nm channel length (L_ch) MoS₂ FET with a drain current (I_ds) of 460 μA/μm at V_ds = 1.6 V, which is twice the best value reported so far on MoS₂ FETs.

Mapping Defect Density in MBE Grown

Growing good quality III-V epitaxial layers on Si substrate is of utmost importance to produce next generation high-performance devices in a cost effective way. In this paper, using physical analysis and electrical measurements of Esaki diodes, fabricated using molecular beam epitaxy grown In0.53Ga0.47As layers on Si substrate, we show that the valley current density is strongly correlated with the underlying epi defect density. Such a strong correlation indicates that the valley characteristics can be used to monitor the epi quality. A model is proposed to explain the experimental observations and is validated using multiple temperature diode I-V data. An excess defect density is introduced within the device using electrical and mechanical stress, both of which are found to have a direct impact on the valley current with a negligible change in the peak current characteristics, qualitatively supporting the model predictions.

{\rm In}_{0.53}{\rm Ga}_{0.47}{\rm As}

We report a record low contact resistivity of sub-1.0×10^-8 Ω.cm² realized on n⁺ In_0.53Ga_0.47As fin sidewall surfaces. This is achieved with VLSI processed fin TLM structures on wafer scale III-V on Si substrates. A novel low-damage III-V fin etch was developed and fins down to 35 nm were fabricated. A surface treatment to smoothen the fin sidewall surfaces was proposed, which reduced sidewall surface roughness variation by 90%. Additionally, we show for the first time that implant temperature could be used to eliminate implant damage in III-V fins. This increased activation efficiency (+3.6×) and reduced sheet resistance (-60%).

Epitaxial Layers on Si Substrate Using Esaki Diode Valley Characteristics

A conformal, chemical-based sulfur monolayer doping process (thereafter S-MLD) on In_xGa_1-xAs (x = 0.53) material is reported. Ultra-shallow junction (x_j <; 10 nm) and low sheet resistance R_s <; 200 Ω/ is demonstrated with bulk activation > 80% at sulfur concentration of >10¹⁹/cm³.

Ultra low contact resistivity ( −8 Ω-cm 2 ) to In 0.53 Ga 0.47 As fin sidewall (110)/(100) surfaces: Realized with a VLSI processed III–V fin TLM structure fabricated with III–V on Si substrates

High mobility, narrow band gap group IV and III-V materials are strong contenders to replace strained-Si channels for logic applications beyond the 16 nm node [1–3]. While there are many research efforts evaluating III-V channels in HEMT and MOSFET forms, model based understanding and control of the FET properties such as channel mobility, series resistance, and off-state leakage are still lacking [4–8]. In this work, we address the aforementioned issues, by investigating laser annealing to control thermal budget and lower series resistance. Additionally we also report on preliminary material analysis and demonstrate the low temperature measurement to the performance of In<inf>0.53</inf>Ga<inf>0.47</inf>As MOSFETs. The electrical and material characteristics of TaN/ZrO<inf>2</inf>/In<inf>0.53</inf>Ga<inf>0.47</inf>As self-aligned n-MOSFETs with high I<inf>on</inf>/I<inf>off</inf> (> 5×10⁴), high mobility (~ 3000 cm /V•sec) and promise for low R<inf>ext</inf> are presented and discussed.

Sub-10nm junction in InGaAs with sulfur mono-layer doping

Advanced, fully depleted devices such as FinFET or Tri-Gate transistors are increasingly sought after to enable density and gate length (Lg) scaling in future technology nodes. As gate-pitch scaling continues, the fin pitch must also be reduced to maintain proper electrostatics control in short Lg devices. However, in the absence of proper junction engineering, further scaling of Lg below 10nm would compromise off-state leakage (Ioff) due to degraded drain-induced barrier lowering (DIBL) and subthreshold slope (SS) as a result of poor short channel control. This may be mitigated by scaling the gate dielectric thickness to maintain good control of short-channel effects (SCE), but it leads to an exponentially increasing gate leakage current and power consumption. Increasing channel doping could be an alternative to improve SCE, but it decreases carrier mobility due to impurity scattering and gives rise to random dopant fluctuations (RDF) issue. Additionally, decreasing the fin pitch to preserve short channel integrity reduces the source/drain (S/D) contact area which leads to an increase in external parasitic resistance (Rext) that has become a critical technology barrier to achieving ITRSs performance target in advanced nodes.

Reducing R ext in laser annealed enhancement-mode In 0.53 Ga 0.47 As surface channel n-MOSFET

We reported double-gate transistors with reduced source-drain (SD) resistance with aluminum (Al) implant on S/D for sub 22 nm technology node1. Al implanted S/D can provide to modulate the electron barrier height of PtSi towards the conduction band. We also investigate Schottky barrier modulation using a new Ge ion implantation (I/I) and segregation approach and the impact of spike anneal on the SBH tuning. Novel silcide alloys of Ni with Yb or Er can be adopted for a FinFET structure. These techniques attribute constitute a simple non-planar cMOS integration sequence with enhanced drive current for future high performance technology nodes.