Alan Kwentus

A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range

This paper describes the architecture and the IC implementation of a direct digital frequency synthesizer (DDFS) that is based on an angle rotation algorithm (similar to CORDIC). It is shown that the architecture can be implemented as a multiplierless, feedforward, and easily pipelineable datapath. A prototype IC has been designed, fabricated in 1.0-/spl mu/m CMOS, and tested. The IC produces 16-b sine and cosine outputs with a spurious-free dynamic range of more than 100 dBc. A 36-b frequency control word gives a tuning resolution of 0.0015 Hz at a 100-MHz sampling rate.

A single-chip universal digital satellite receiver with 480 MHz IF input

A complete single-chip universal digital satellite receiver supports all current DBS system standards. The mixed signal device accepts a modulated data stream at up to 90 Mb/s and delivers a demodulated error-corrected output data stream. The IC features an analog front-end with 480 MHz IF downconversion and dual 8 bit A/D converters, an all-digital BPSK/QPSK/OQPSK receiver, and a DVB/DSS/DigiCipher-II compliant concatenated Viterbi/Reed-Solomon FEC decoder with on-chip deinterleaver RAM. All required clocks are generated on chip from a single reference crystal. The chip contains 1.2 M transistors in a 22 mm/sup 2/ die in single-poly 0.35 /spl mu/m CMOS with four layers of metal.