Avanindra Madisetti

A 100-MHz, 16-b, direct digital frequency synthesizer with a 100-dBc spurious-free dynamic range

This paper describes the architecture and the IC implementation of a direct digital frequency synthesizer (DDFS) that is based on an angle rotation algorithm (similar to CORDIC). It is shown that the architecture can be implemented as a multiplierless, feedforward, and easily pipelineable datapath. A prototype IC has been designed, fabricated in 1.0-/spl mu/m CMOS, and tested. The IC produces 16-b sine and cosine outputs with a spurious-free dynamic range of more than 100 dBc. A 36-b frequency control word gives a tuning resolution of 0.0015 Hz at a 100-MHz sampling rate.

A 3.125Gbps timing and data recovery front-end with adaptive equalization

A 3.125Gbps timing and data recovery front-end is described. Adaptive discrete-time analog forward equalizers implemented in the receiver are used to cancel intersymbol interference. The coefficients in the analog equalizers are continuously adjusted by a digital adaptation loop. To save power, the digital adaptation loop operates at a 32/spl times/ subsample rate. The timing recovery is 2/spl times/ oversampled and uses these equalizers in its path for robust performance in the presence of intersymbol interference. A quad 3.125Gbps transceiver core has been fabricated in a standard 0.18 /spl mu/m CMOS process.