Alan Ristow

Development of a Methodology for Improving Photovoltaic Inverter Reliability

In evaluating the energy-generation potential of a photovoltaic (PV) energy system, the system is usually assumed to work without interruptions over its entire life. PV energy systems are fairly reliable, but as any complex system, they may fail. In PV systems, the inverter is responsible for the majority of failures, and most inverter failures are blamed on the aluminum electrolytic capacitors typically used in the dc bus. This paper investigates the effects of common failure modes on the reliability of PV inverters and suggests a model framework for decomposing the inverter into subsystems for more detailed study. The challenges of statistical analysis based on small data sets are discussed, and simulations are performed to illustrate the proposed model using a simple decomposition into subsystems of the inverter used in the 342-kW PV system at the Georgia Tech Aquatic Center.

Greater Than 16% Efficient Screen Printed Solar Cells on 115-170 μm Thick Cast Multicrystalline Silicon

In this paper we report on the impact of mc-Si wafer thickness on efficiency. We have obtained 16.8%, 16.4%, 16.2% and 15.7% efficient screen printed 4 cm2 solar cells on 280 mum, 170 mum, 140 mum and 115 mum thick cast mc-Si respectively. Analysis of these cells showed that the efficiency of the 115 mum thick cell is limited by a BSRV of 750 cm/s, FSRV of 120,000 cm/s and a BSR of 67%. A module manufacturing cost model for a 25 MW plant was used to demonstrate that 15.7% efficient cells on 115 mum thick wafers are more cost effective than 16.8% cells on 280 mum wafers. The module manufacturing cost reduced from

Rapid thermal processing of next generation silicon solar cells

1.82/W to

Review and comparison of equations relating bulk lifetime and surface recombination velocity to effective lifetime measured under flash lamp illumination

1.63/W when the wafer thickness was reduced from 280 mum (efficiency 16.8%) to 115 mum (efficiency 15.7%). A roadmap is developed for 115 mum thick wafers to demonstrate how cell efficiency can be increased to greater than 18% resulting in a module cost of less than

Screen-Printed Back Surface Reflector for Light Trapping in Crystalline Silicon Solar Cells

1.40/W

Guidelines for More Accurate Determination and Interpretation of Effective Lifetime from Measured Quasi-Steady-State Photoconductance

Rapid and potentially low-cost process techniques are analyzed and successfully applied towards the fabrication of high-efficiency mono- and multicrystalline Si solar cells. First, a novel dielectric passivation scheme (formed by stacking a plasma silicon nitride film on top of a rapid thermal oxide layer) is developed that serves as antireflection coating and reduces the surface recombination velocity (Seff) of the 1˙3 Ω-cm p-Si surface to approximately 10 cm/s. The essential feature of the stack passivation scheme is its ability to withstand short 700 – 850°C anneal treatments used to fire screen printed (SP) contacts, without degradation in Soeff. The stack also lowers the emitter saturation current density (Joe) of 40 and 90 Ω/□ emitters by a factor of three and 10, respectively, compared to no passivation. Next, rapid emitter formation is accomplished by diffusion under tungsten halogen lamps in both belt line and rapid thermal processing (RTP) systems (instead of in a conventional infrared furnace) . Third, a combination of SP aluminium and RTP is used to form an excellent back surface field (BSF) in 2 min to achieve an effective back surface recombination velocity (Seff) of 200 cm/s on 2˙3 Ω-cm Si. Finally, the above individual processes are integrated to achieve: (1) >19% efficient solar cells with emitter and Al-BSF formed by RTP and contacts formed by vacuum evaporation and photolithography, (2) 17% efficient manufacturable cells with emitter and Al-BSF formed in a belt line furnace and contacts formed by SP. Copyright