Albert H. Taddiken

Co-integration of GaAs MESFET and Si CMOS circuits

Co-integration of GaAs MESFET and Si CMOS circuits is demonstrated using GaAs-on-Si epitaxial growth on prefabricated Si wafers. This is thought to be the first report of circuit-level integration of the two types of devices in a coplanar structure. A 2- mu m gate Si CMOS ring oscillator has shown a minimum delay of 570 ps/gate, whereas on the same wafer a 1- mu m gate GaAs MESFET buffered-FET-logic (BFL) ring oscillator has a minimum delay of only 70 ps/gate. A composite ring oscillator consisting of Si CMOS invertors and GaAs MESFET invertors connected in a ring has been successfully fabricated.<<ETX>>

A low on-resistance, high-current GaAs power VFET

We have developed a new fabrication process for GaAs VFETs that results in excellent performance in a 10 A prototype designed for switching in low voltage synchronous rectifier applications. The new fabrication process uses a buried carbon-doped GaAs gate structure for the gate electrodes and an epitaxial overgrowth step. We have demonstrated 10 A devices with 3.5 cm of gate width and 1.5 mohm of on-resistance (specific on-resistance of 84 /spl mu/ohm-cm/sup 2/). The device required a 0.5 /spl mu/m channel etched between 0.5 /spl mu/m gates placing stringent requirements on the gate side wall etch profile and epitaxial doping uniformity.<<ETX>>

GaAs E/D MESFET 1-kbit static RAM fabricated on silicon substrate

A GaAs enhancement/depletion (E/D) MESFET 1-kbit static RAM has been fabricated on a 2-in GaAs-on-Si substrate. This is the most complex GaAs circuit reported to date for GaAs-on-Si material. The GaAs layer is grown on a

Co-integrated resonant tunneling and heterojunction bipolar transistor full adder

We present the first resonant tunneling bipolar transistor integrated circuits operating at room temperature. The circuits are comprised of co-integrated resonant tunneling and double heterojunction bipolar transistors based on III-V heteroepitaxy on InP substrates. The resonant tunneling bipolar transistors exhibit a peak-to-valley collector current ratio exceeding 70 which is higher than previous room temperature reports. Using this technology we demonstrate a 3-transistor XNOR, a 6-transistor XOR, a 5-transistor CARRY, and a 17-transistor full adder, all using a 3 V supply.<<ETX>>

Multiple-valued logic computation circuits using micro- and nanoelectronic devices

The advantages of the negative transconductance of the resonant tunneling transistor (RTT) for implementing very efficient multivalued-logic (MVL) arithmetic building blocks are examined. Full adders are described for both the positive-digit 2.4 redundant number system and the signed-digit 4.3 minimum-redundant number system. The outlook for nanoelectronic MVL is considered.<<ETX>>

GaAs MESFET and Si CMOS cointegration and circuit techniques

The cointegration of GaAs MESFET and Si CMOS circuits on a single chip has recently been achieved using GaAs-on-Si epitaxial growth techniques. The authors discuss the device and circuit aspects of GaAs/Si cointegration and describe some circuit techniques for monolithically interfacing between GaAs MESFET and Si CMOS circuits. The cointegration was realized in a planar structure appropriate for IC (integrated circuit) processing, which allows interconnection of the two types of circuits by conventional metal interconnects. Specifically, the process was demonstrated by fabricating composite ring oscillators consisting of GaAs MESFET BFL (buffered FET logic) inverters and Si CMOS inverters connected in a ring.<<ETX>>

Co-integration of resonant tunneling and double heterojunction bipolar transistors on InP

The authors report the first co-integration of resonant tunneling and heterojunction bipolar transistors. Both transistors are produced from a single epitaxial growth by metalorganic molecular beam epitaxy, on InP substrates. The fabrication process yields 9- mu m/sup 2/-emitter resonant tunneling bipolar transistors (RTBTs) operating at room temperature with peak-to-valley current ratios (PVRs) in the common-emitter transistor configuration, exceeding 70, at a resonant peak current density of 10 kA/cm/sup 2/, and a differential current gain at resonance of 19. The breakdown voltage of the In/sub 0.53/Ga/sub 0.47/As-InP base/collector junction, V/sub CBO/, is 4.2 V, which is sufficient for logic function demonstrations. Co-integrated 9- mu m/sup 2/-emitter double heterojunction bipolar transistors (DHBTs) with low collector/emitter offset voltage, 200 mV, and DC current gain as high as 32 are also obtained. On-wafer S-parameter measurements of the current gain cutoff frequency (f/sub T/) and the maximum frequency of oscillation (f/sub max/) yielded f/sub T/ and f/sub max/ values of 11 and 21 GHz for the RTBT and 59 and 43 GHz for the HBT, respectively.<<ETX>>

Monolithic process for co-integration of GaAs MESFET and silicon CMOS devices and circuits

A monolithic process to cointegrate Si CMOS and GaAs MESFET devices and circuits on a silicon chip through epitaxial growth of a GaAs layer on a prefabricated Si wafer is described. By embedding the GaAs layer in Si recesses in selected regions of a Si wafer, the cointegration has been realized in a coplanar structure appropriate for IC processing. On a monolithically integrated wafer, a 2- mu m gate length Si CMOS ring oscillator showed a minimum delay of 570 ps/gate, and a 1- mu m gate GaAs MESFET BFL ring oscillator had a minimum delay of 68 ps/gate. These results indicate that the individual device speed is not degraded by monolithic integration. Some changes in threshold voltage, however, were observed for Si CMOS devices after the GaAs device fabrication. A composite ring oscillator consisting of a string of Si CMOS inverters and a string of GaAs MESFET inverters connected in a ring has been successfully fabricated. >

Nanoelectronic circuits using resonant tunneling transistors and diodes

Integration of RTDs (resonant tunneling diodes) into one or more terminals of conventional transistors has led to a large family of resonant tunneling transistors. These include the resonant tunneling bipolar transistor (RTBT) and the resonant tunneling hot electron transistor (RHET). These devices are fabricated by placing RTDs in the emitter contact of heterojunction bipolar or hot electron transistors, respectively. Another unique nanoelectronic device is the bipolar quantum-well resonant tunneling transistor (BiQuaRTT), which is a heterojunction bipolar transistor (HBT) with a quantum-well structure incorporated into the base-collector junction. Negative transconductance devices, such as the RTBT, can be used to implement single-transistor logic gates. The RTBT characteristic can be enhanced to provide multiple negative transconductance regions by adding additional RTDs in the emitter epitaxial stack.<<ETX>>

Design and application of a GaAs digital RF memory chip

The design and performance of a GaAs integrated memory/logic chip designed for digital RF memory (DRFM) applications is described. This chip, called a programmable delay-line element (PDLE), implements the basic DRFM storage and delay functions. The RAM-with-logic configuration combines a 4-kb static RAM with 750 logic gates, providing on a single chip the components for storage, address generation, demultiplexing, multiplexing, and control functions normally provided by a variety of separate chips. A distributed control organization, where the chip is configured to provide as outputs all the signals required as inputs to another identical chip, is used. Chips cascaded into strings implement the programmable delay lines required for DRFM systems. Problems associated with complex signal distribution networks are avoided since, within a string, signal distribution requires only local interconnections between adjacent chips. Correct operation of all functions was demonstrated in a four-chip string which provides a total memory capacity of 16 kb. The maximum sampling rate was 800 MHz, and power dissipation was approximately 2 W per chip. >