H. Shichijo

Anomalous leakage current in LPCVD PolySilicon MOSFET's

The anomalous leakage current ILin LPCVD polysilicon MOSFETs is attributed to field emission via grain-boundary traps in the (front) surface depletion region at the drain, and an analytic model that describes the strong dependences of ILon the gate and drain voltages is developed. The model predictions are consistent with measured current-voltage characteristics. Physical insight afforded by the model implies device design modifications to control and reduce IL, and indicates when the back-surface leakage component is significant.

Negative differential resistance through real‐space electron transfer

A new mechanism is proposed to obtain negative differential resistance in layered heterostructures for conduction parallel to the interface. The mechanism is based on hot‐electron thermionic emission from high‐mobility GaAs into low‐mobility AlxGa1−xAs. Preliminary calculations indicate that high peak‐to‐valley ratios can be achieved. The transfer speed is estimated to be of the order of 10−11 s. We further show that the concept of hot‐electron thermionic emission can be applicable to a variety of devices.

Characteristics and three-dimensional integration of MOSFET's in small-grain LPCVD polycrystalline Silicon

Building on nearly two decades of reported results for MOSFETs fabricated in small-grain polycrystalline silicon, a design methodology is developed that yields devices which have low threshold voltage, high drive current, low leakage current, tight parameteric control, and reduced topology, while requiring no nonstandard materials, processes, and tools. Design criteria and device performance are discussed, grain boundary characterization techniques are described, technological issues pertinent to VLSI implementation are investigated, and long-term device reliability is studied. The potential applications of the polysilicon MOSFETs in high-density dRAM and sRAM are explored. The successful implementation of an experimental stacked CMOS 64K static RAM proves the utility of these devices for three-dimensional integration in a VLSI environment.

Defect reduction by thermal annealing of GaAs layers grown by molecular beam epitaxy on Si substrates

Post growth thermal annealing has been used to reduce the defect density of GaAs layers grown on Si substrates by molecular beam epitaxy. Transmission electron microscopy indicates a 100× reduction of the true defect density. Twins and stacking faults were eliminated entirely. Most misfit dislocations were confined within the first ∼150 A GaAs layer and formed a regular and narrow network along the Si/GaAs interface. Similar results were obtained from an ion implanted and annealed specimen.

A trench transistor cross-point DRAM cell

A 1T DRAM cell with both the transistor and the capacitor fabricated on the sidewalls of a deep trench is described. Trench Transistor Cell (TTC) fabrication and characterization are discussed.

Device and technology evolution for Si-based RF integrated circuits

The relationships between device feature size and device performance figures of merit (FoMs) are more complex for radio frequency (RF) applications than for digital applications. Using the devices in the key circuit blocks for typical RF transceivers, we review and give trends for the FoMs that characterize active and passive RF devices. These FoMs include transit frequency at unity current gain f/sub T/, maximum frequency of oscillation f/sub MAX/ at unit power gain, noise, breakdown voltage, capacitor density, varactor and inductor quality, and the like. We use the specifications for wireless communications systems to show how different Si-based devices may achieve acceptable FoMs. We focus on Si complementary metal-oxide-semiconductor (CMOS), Si Bipolar CMOS, and Si bipolar devices, including SiGe heterojunction bipolar transistors, RF devices, and integrated circuits (ICs). We analyze trends in the FoMs for Si-based RF devices and ICs and show how these trends relate to the technology nodes of the 2003 International Technology Roadmap for Semiconductors. We also compare FoMs for the best reported performance of research devices and for the performance of devices manufactured in high volumes, typically more than 10 000 devices. Certain commercial equipment, instruments, or materials are identified in this article to specify adequately the experimental or theoretical procedures. Such identification does not imply recommendation by any of the host institutions of the authors, nor does it imply that the equipment or materials are necessarily the best available for the intended purpose.

Carrier collection in a semiconductor quantum well

Data are presented showing that a GaAs quantum well, sandwiched between two epitaxial AlxGa1-xAs(x ∼ 0.4) confining layers, loses its effectiveness as a collector of excess carriers and as a source of recombination radiation for well dimensions Lz < 100 A. It is shown that this behavior is expected because of the difficulty in scattering carriers to the bottom of the quantum well as Lz → lp, the path length for scattering (LO phonon).

A 4-Mbit DRAM with trench-transistor cell

An experimental 5-V-only 1M-word/spl times/4-bit dynamic RAM with page and SCD modes has been built in a relatively conservative 1-/spl mu/m CMOS technology with double-level metal and deep trenches. It uses a cross-point one-transistor trench-transistor cell that measures only 9 /spl mu/m/SUP 2/. A double-ended adaptive folded bit-line architecture used on this DRAM provides the breakthrough needed to take full density advantage of this cross-point cell. The 30-fF storage capacitance of this cell is expected to provide high alpha immunity since the charge is stored in polysilicon and is oxide isolated from the substrate. A 150-ns now-address-stable access time and 40-ns column-address-strobe access time have been observed.

RF CMOS on high-resistivity substrates for system-on-chip applications

The use of a high-resistivity substrate extends the capability of standard digital CMOS technology to enable the integration of high-performance RF passive components. The impact of substrate resistivity on the key components of RF CMOS for system-on-chip (SoC) applications is discussed. The comparison includes the transistor, transmission line, inductor, capacitor and varactor, as well as the noise isolation. We also discuss the integration issues including latch-up and well-well isolation in a 0.35-/spl mu/m Cu metal pitch, 0.1-/spl mu/m-gate-length RF CMOS technology.

Co-integration of GaAs MESFET and Si CMOS circuits

Co-integration of GaAs MESFET and Si CMOS circuits is demonstrated using GaAs-on-Si epitaxial growth on prefabricated Si wafers. This is thought to be the first report of circuit-level integration of the two types of devices in a coplanar structure. A 2- mu m gate Si CMOS ring oscillator has shown a minimum delay of 570 ps/gate, whereas on the same wafer a 1- mu m gate GaAs MESFET buffered-FET-logic (BFL) ring oscillator has a minimum delay of only 70 ps/gate. A composite ring oscillator consisting of Si CMOS invertors and GaAs MESFET invertors connected in a ring has been successfully fabricated.<<ETX>>