Albert Theuwissen

Adaptive pixel defect correction

Although the number of pixels in image sensors is increasing exponentially, production techniques have only been able to linearly reduce the probability that a pixel will be defective. The result is a rapidly increasing probability that a sensor will contain one or more defective pixels. Sensors with defects are often discarded after fabrication because they may not produce aesthetically pleasing images. To reduce the cost of image sensor production, defect correction algorithms are needed that allow the utilization of sensors with bad pixels. We present a relatively simple defect correction algorithm, requiring only a small 7 by 7 kernel of raw color filter array data that effectively corrects a wide variety of defect types. Our adaptive edge algorithm is high quality, uses few image lines, is adaptable to a variety of defect types, and independent of other on-board DSP algorithms. Results show that the algorithm produces substantially better results in high-frequency image regions compared to conventional one-dimensional correction methods.

Influence of terrestrial cosmic rays on the reliability of CCD image sensors

An aging effect in solid-state image sensors is studied: the generation of hard errors resulting in hot spots or white pixels. These effects even occur in sensors that are stored on the shelf. This paper describes experiments that are conducted to prove that the main origin can be found with neutrons that are part of terrestrial cosmic rays

An image sensor of 1,000,000 fps, 300,000 pixels, and 144 consecutive frames

An image sensor for an ultra-high-speed video camera was developed. The maximum frame rate, the pixel count and the number of consecutive frames are 1,000,000 fps, 720 x 410 (= 295,200) pixels, and 144 frames. A micro lens array will be attached on the chip, which increases the fill factor to about 50%. In addition to the ultra-high-speed image capturing operation to store image signals in the in-situ storage area adjacent to each pixel, standard parallel readout operation at 1,000 fps for full frame readout is also introduced with sixteen readout taps, for which the image signals are transferred to and stored in a storage device with a large capacity equipped outside the sensor. The aspect ratio of the frame is about 16 : 9, which is equal to that of the HDTV format. Therefore, a video camera with four sensors of the ISIS-V4, which are arranged to form the Bayer’s color filter array, realizes an ultra-high-speed video camera of a semi-HDTV format.

The hole role

The importance of holes in solid-state image sensors is described. Todays success of digital imaging is based on the positive effect of an accumulation layer that reduces the interface-related dark current and dark current fixed-pattern noise. This superb imaging feature is applied in CCD as well as in CMOS devices, in consumer as well as in professional equipment. Holes are not only used to improve the dark performance of imagers, other examples are fixing electrostatic potentials, creating gate structures, draining photon-generated charges and constructing output-amplifier stages

Two calibration methods to improve the linearity of a CMOS image sensor

This paper presents two on-chip calibration methods for improving the linearity of a CMOS image sensor (CIS). A prototype 128 × 128 pixel sensor with a size of 10 μm×12 μm is fabricated using a 0.18 μm 1P4M CIS process. Both calibration methods show obvious improvement on the linearity of the CIS. Compared with the voltage mode (VM) calibration, the pixel mode (PM) calibration method achieves better linearity results by improving the nonlinearity of the CIS 26×. This results in a minimum nonlinearity of 0.026%, which is a 2× better than the state-of-the-art.

Linearity analysis of a CMOS image sensor

In this paper, we analyze the causes of the nonlinearity of a voltage-mode CMOS image sensor, including a theoretical derivation and a numerical simulation. A prototype chip designed in a 0.18 μm 1-poly 4-metal CMOS process technology is implemented to verify this analysis. The pixel array is 160 × 80 with a pitch of 15 μm, and it contains dozens of groups of pixels that have different design parameters. From the measurement results, we confirmed these factors affecting the linearity and can give guidance for a future design to realize a high linearity CMOS image sensor.

A comparative noise analysis and measurement for n-type and p-type pixels with CMS technique

This paper presents a noise analysis and noise measurements of n-type and p-type pixels with correlated multiple sampling (CMS) technique. The output noise power spectral density (PSD) of both pixel types with different CMS noise reduction factors have been simulated and calculated in the spectral domain. For validation, two groups of test pixel have been fabricated with a state-of-the-art n-type and p-type CMOS image sensor (CIS) technology. The calculated and the measured noise results with CMS show a good agreement. Measurement results also show that the n-type and p-type pixels reach a 1.1 e and 0.88 h inputreferred temporal noise respectively with a board-level 64 times digital CMS and ×6 analog gain.

Simulation-based development and characterization of a CCD architecture for 1 million frames per second

A new high-speed CCD-sensor, capable of capturing 103 consecutive images at a speed of 1 million frames per second, was developed by the authors. To reach this high frame-rate, 103 CCD-storage-cells are placed next to each image-pixel. Sensors utilizing this on-chip-memory-concept can be called In-situ Storage Image Sensor or ISIS. The ISIS is build in standard CCD-technology. To check if this technology could be used for an ISIS, a test sensor called ISIS V1 was designed first. The ISIS V1 is just a simple modification of an existing standard CCD-sensor and it is capable of taking 17 consecutive images. The new sensor called ISIS V2 is a dedicated design in the existing technology. It is equipped with storage CCD-cells that are also used in the standard CCD-sensor, large light-sensitive pixels, an overwriting mechanism to drain old image information and a CCD-switch to use a part of the storage cells also as vertical read-out registers. Nevertheless, the new parts in the architecture had to be simulated by a 3-D device simulator. Simulation results and characteristic parameters of the ISIS-CCD as well as applications of the camera are given.