Alberto Pagani

Thermal issues in test: An overview of the significant aspects and industrial practice

Thermal phenomena occurring along test execution at the final stages of the manufacturing flow are considered as a significant issue for several reasons, including dramatic effects like circuit damage that is leading to yield loss. This paper tries to redeem those bad guys in order to exploit them to improve the test quality, reducing the overall test cost without affecting the yield.

Electro Optical Terahertz Pulse Reflectometry, a non destructive technique to localize defects on various type of package

Abstract Localizing defects (particularly, dead open and resistive open defects) at package level is becoming a critical challenge for Failure Analysis Laboratories due to package miniaturisation and increased complexity. One of the well-known approaches to address this set of problems within a Device Under Test (DUT) is Time Domain Reflectometry (TDR). The main limitation of this technique is the lack of distance-to-defect accuracy and sensitivity. Electro Optical Terahertz Pulse Reflectometry (EOTPR) overcomes these limitations by using photoconductive terahertz generation and detection technology, resulting in a system with: (i) high measurement bandwidth, (ii) extremely low time base jitter, and (iii) high time base accuracy and range with greater sensitivity. In this paper we present case studies in which EOTPR has been successfully applied to a series of different device types.

A comprehensive methodology for stress procedures evaluation and comparison for Burn-In of automotive SoC

Environmental and electrical stress phases are commonly applied to automotive devices during manufacturing test. The combination of thermal and electrical stress is used to give rise to early life latent failures that can be naturally found in a population of devices by accelerating aging processes through Burn-In test phases. This paper provides a methodology to evaluate and compare the stress procedures to be run during Burn-In; the proposed method takes into account several factors such as circuit activity, chip surface temperature and current consumption required by the stress procedure, and also considers Burn-In flow and tester limitations. A specific metric called Stress Coverage is suggested summing up all the stress contributions. Experimental results are gathered on an automotive device, showing the comparison between scan-based and functional stress run by a massively parallelized test equipment; reported figures and tables quantify the differences between the two approaches in terms of stress.