Alejandro Díaz Sánchez

Voltage Regulation System for UHF RFID Tags

This paper presents the design of a Voltage Regulation System for UHF Passive RFID Tags which consists of a Clamp Circuit and LDO Voltage Regulator. The Clamps current consumption is 100nA and 1μA when the voltage reaches levels of 2.6V and 3.6V, respectively. LDO Voltage Regulator is capable of supplying a load current of 4.5 μA with only a current consumption of 900nA. The LDO Voltage Regulator has an overall efficiency of 73%, provides a load regulation of 25.53mV/μA and a settling time of 4μs. The design, simulation and layout are realized using 0.50 μm technology ON-SEMI two poly - three metal.

4 channel signal based FPGA architecture for myolectric features extraction by H.O.S.

In this paper, an FPGA-based parallel architecture for the computation of myoelectric signal feature extraction, employing higher order statistics in presented. The three channels myoelectric signal is obtained directly from the users muscles, in order to obtain prosthesis movement commands which emulate a biological elbow. The proposed architecture was realized in Very High Speed Integrated Circuit (BHSIC) by Hardware Description Language (VHDL), and functionally verified on a Xilinx board, which uses a Spartan-3 XC3S700AN FG48-4 FPGA. Experimental results are presented, and establish a maximum operation frequency of 44.570MHz.