Luis Abraham Sánchez-Gaspariano

Accuracy vs simulation speed trade-off enhancements in the generation of chaotic attractors

In this paper, the trade-off between accuracy and simulation speed in the generation of muti-scroll chaotic attractors at 1-D is analyzed and improved. In a first step, a macromodel based on bipolar transistors and passive elements is used to model the behavior of Opamps, and later on they are used to approach the behavior of all nonlinear system. Hspice simulations are executed to generate chaotic attractors in the phase plane and time-series. CPU-time used during the solution of the chaotic system is computed. In a second stage, a simple and accurate nonlinear model, which includes the most influential performance parameters for Opamps, is coded in C++ and it is used to generate a nonlinear system of equations, which models the behavior of all chaotic system. CPU-time is also computed. Because chaotic waveforms generated have a random behavior, statistical tests are used to measure the similitude/accuracy between two random variables during a long time. Our results indicate that chaotic waveforms can swiftly be generated by using the simple but accurate model for Opamps without the accuracy worsens, independently of the initial conditions of the chaotic system.

Application of a Chaotic Oscillator in an Autonomous Mobile Robot

Abstract Terrain exploration robots can be of great usefulness in critical navigation circumstances. However, the challenge is how to guarantee a control for covering a full terrain area. That way, the application of a chaotic oscillator to control the wheels of an autonomous mobile robot, is introduced herein. Basically, we describe the realization of a random number generator (RNG) based on a double-scroll chaotic oscillator, which is used to guide the robot to cover a full terrain area. The resolution of the terrain exploration area is determined by both the number of bits provided by the RNG and the characteristics of step motors. Finally, the experimental results highlight the covered area by painting the trajectories that the robot explores.

On the Electronic Realizations of Fractional-Order Phase-Lead-Lag Compensators with OpAmps and FPAAs

It is well known that the fractional-order phase-lead-lag compensators can achieve control objectives that are not always possible by using their integer-order counterparts. However, up to now one can find only a few of publications discussing the strategies for parameters’ tuning of these compensators, with only simulation results reported. This is due in part to the implicit difficulties on the implementation of circuit elements with frequency responses of the form \(s^{\pm \lambda }\) that are named “fractances”. In this regard, there exist approximations with rational functions, but the drawback is the difficulty to approximate the required values with the ones of the commercially-available resistances and capacitors. Consequently, fractional compensators have not been appreciated by the industry as it is in the academia. Therefore, motivated by the lack of reported implementations, this chapter is structured as a tutorial that deals with the key factors to perform, with the frequency-domain approach, the design, simulation and implementation of integer-order and fractional-order phase-lead-lag compensators. The circuit implementations are performed with Operational Amplifiers (OpAmps) and with Field Programmable Analog Arrays (FPAA). Emphasis is focused in the obtaining of commercially-available values of resistances and capacitors. Therefore, the design procedure starts with the use of equations that provide the exact and unique solution for each parameter of the compensator, avoiding conventional trial-and-error procedures. Then, five OpAmp-based configurations for integer-order and fractional-order realizations are described in terms of basic analog building blocks, such as integrators or differential amplifiers, among others. The corresponding design equations are also provided. Then, six examples are presented for both, OpAmp-based and FPAA-based implementations with the simulation and experimental results discussed regarding other results reported in the literature.

Improving linearity in MOS varactor based VCOs by means of the output quiescent bias point

This paper presents a CMOS based LC tank VCO topology improving the tuning range linearity. The VCO tuning range is linearized with PMOS varactors which remain in the inversion region for an extended range of the control voltage. This is achieved with the design of the quiescent operating point in the VCOs output nodes with a value close to the voltage rails, letting the varactors to behave quasi linearly in the achievable VCO tuning range. The experimental results of a VCO in a CMOS 0.35m process show a linear tuning range improvement of 75% of the control voltage in the (1.431.55)GHz range, with a minimum VCO gain variation compared to similar architectures. The results show a phase noise improvement from 94dBc/Hz to 124dBc/Hz @600kHz offset from the carrier with an overall reduced amplitude noise for the VCO. HighlightsThe VCO shows an improvement of linearity for the tuning range.The improvement is a consequence of the output quiescent point design.The comparison includes the VCO gain linearity, not considered in many works.Experimental results in a CMOS 0.35um attest the improvement in linearity.

A compact CMOS Class-AB analog median filter

A power efficient implementation of a CMOS Class-AB analog median filter is presented. The median detector is based on transconductance comparators accomplished with new Differential Flipped Voltage Followers. The followers employ a current comparator to switch-on an auxiliary transistor to drive additional current whenever it is required, performing Class-AB operation. Area is saved by taking advantage of the large impedance node of the current comparator to accomplish Miller frequency compensation. Simulation results using the ON-SEMI 0.5 μm technology parameters validate the proposed structure.