Alejandro Nicolás

Automatic synthesis of embedded SW for evaluating physical implementation alternatives from UML/MARTE models supporting memory space separation

Abstract The proposed approach presents a method for automatically synthesizing the SW code of complex embedded systems from a model-driven system specification. The solution is oriented to enabling easy exploration and design of different allocations of SW components in heterogeneous platforms, minimizing designer effort. The system is initially described following the UML/MARTE standard. Applying this standard, the system is modeled, describing its components, interfaces and communication links, the system memory spaces, the resource allocations and the HW architecture. From that information, a SW infrastructure containing the communication infrastructure is generated ad-hoc for the system depending on the HW architecture and the resource allocations evaluated. The consequent communication overhead reduction can result in an important advantage for system performance optimization.

Automatic synthesis from UML/MARTE models using channel semantics

Model-driven design is very common nowadays. In this context, the UML/MARTE profile is a well-known solution for real-time, embedded system modeling. This profile enables the functional and non-functional details of the system to be modeled together. Regarding non-functional details, the profile allows certain real-time constraints to be imposed when describing the system concurrency, in order to ensure predictability. However, these constraints also limit the modeling flexibility required to evaluate different design alternatives when optimizing system performance. The paper proposes a solution for automatically synthesizing the resulting models, combining new communication semantics with standard UML/MARTE real-time management features. The UML/MARTE approach presented in this paper enables concurrency and synchronization effects to be modeled at communication points, making system exploration and implementation easier.

Automatic deployment of component-based embedded systems from UML/MARTE models using MCAPI

The increasing complexity in the development of embedded system is raising the need of system modularization, parallelization and component portability. High-level languages such as UML are clearly oriented to solve these needs, but implementation flows are usually highly dependent on platform details. Different platform-agnostic APIs such as MPI or MCAPI have appeared to increase the application independence from the executive HW. Nevertheless, the gap between the high-level models and the final system implementations is still too large. In this context, this paper presents a methodology for automating system deployment of component-based systems. The process starts from a high level description based on UML/MARTE, including complex channel semantics and provides automatic code generation for interconnection and deployment of system components based on MCAPI. This automatic process enables exploring different possibilities both in the component allocation and in the resulting concurrency, involving low designer effort.

Automatic synthesis of communication and concurrency for exploring component-based system implementations considering UML channel semantics

Nowadays, multi-processor systems play a critical role in embedded system engineering. As a result, the generation of optimal concurrent implementations is an unavoidable but difficult task. Correct concurrent codes achieving maximum performance on the target platform are hard to obtain. On the one hand, dependencies on concurrent computations, such as shared variables or synchronizations, are extremely difficult to analyze from source code. On the other hand, it is completely unfeasible for designers to manually generate multiple implementations in order to evaluate and compare all the possible design alternatives. To overcome these limitations, this paper presents an automatic code generation approach focusing on communication channel semantics. The approach proposes the use of UML/MARTE models to enable designers to graphically handle dependencies and concurrency of the models. As a result, the automatic generation process enables multiple design alternatives to be easily obtained and evaluated without adding manual effort to the design process. To demonstrate these capabilities, the methodology is tested with two large examples.

Improving the design flow for parallel and heterogeneous architectures running real-time applications

In this article, we present the work-in-progress of the EU FP7 PHARAON project, started in September 2011. The first objective of the project is the development of new techniques and tools capable to guide and assist the designer in the development process, from UML specifications to implementation and debug on multicore platform. This tool chain will offer the possibility to propose and implement several parallelization strategies and drive the designer into implementation steps. The second objective of the project is to develop monitoring and control techniques in the middleware of the system capable to automatically adapt platform services to applications requirements and therefore reduce power consumption in a transparent manner for applications.

Automatic Synthesis over Multiple APIs from Uml/Marte Models for Easy Platform Mapping and Reuse

The increasing complexity in the development of embedded system applications is necessitating system modularization, parallelization and component portability. Finding the best solution to combine component reuse and platform optimization is not an easy and straightforward task, especially when considering the different APIs supported to provide communication and concurrency on the different boards. Thus, in order to reduce designer effort, the development of automatic synthesis tools operating from high level models is emerging. In this context, this paper presents a methodology for automating system deployment on different platforms supporting distinct APIs. The process starts from a high-level description based on UML/MARTE and provides automatic code generation for interconnection and deployment of system components. This automatic process enables exploration of different possibilities both in the component allocation and in the resulting concurrency, requiring only minimal designer effort. Different APIs such as POSIX, OpenMP, OpenStream, TCP-IP and MCAPI are covered to provide the required flexibility for platform support and reuse.

On Identities of a Ternary Quaternion Algebra

This article studies a simple 4-dimensional ternary algebra 𝒜 which appears analogously to the quaternions from the Lie algebra 𝔰𝔩(2). We describe the heights 1 and 2 identities, and the derivations of 𝒜. Based on 𝒜, some ternary enveloping algebras for ternary Filippov algebras are constructed.

On skew-symmetric matrices related to the vector cross product in R^7

A study of real skew-symmetric matrices of orders

Parallel Native-Simulation for Multi-processing Embedded Systems

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System level methodology based on VIPPE applied to the implementation of a scalable video decoder on the ZynQ platform

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