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The COMPLEX methodology for UML/MARTE Modeling and design space exploration of embedded systems

The design of embedded systems is being challenged by their growing complexity and tight performance requirements. This paper presents the COMPLEX UML/MARTE Design Space Exploration methodology, an approach based on a novel combination of Model Driven Engineering (MDE), Electronic System Level (ESL) and design exploration technologies. The proposed framework enables capturing the set of possible design solutions, that is, the design space, in an abstract, standard and graphical way by relying on UML and the standard MARTE profile. From that UML/MARTE based model, the automated generation framework proposed produces an executable, configurable and fast performance model which includes functional code of the application components. This generated model integrates an XML-based interface for communication with the tool which steers the exploration. This way, the DSE loop iterations are efficiently performed, without user intervention, avoiding slow manual editions, or regeneration of the performance model. The novel DSE suited modelling features of the methodology are shown in detail. The paper also presents the performance model generation framework, including the enhancements with regard the previous simulation and estimation technology, and the exploration technology. The paper uses an EFR vocoder system example for showing the methodology and for demonstrative results.

The SATURN Approach to SysML-Based HW/SW Codesign

The main obstacle for the wide acceptance of UML and SysML in the design of electronic systems is due to a major gap in the design flow between UML-based modeling and SystemC-based verification. To overcome this gap, we present an approach developed in the SATURN project which introduces UML profiles for the co-modeling of SystemC and C with code generation support in the context of ARTiSAN Studio®. We finally discuss the evaluation of the approach by two case studies.

Generating heterogeneous executable specifications in SystemC from UML/MARTE models

Modeling and analysis of real-time embedded system is becoming an important area of research nowadays. In this context, the UML/MARTE profile has been introduced to support the specification, design, and verification stages in the development process. It provides a wide set of facilities to capture the information required in the refinement steps throughout the design flow. To carry out the actions involved in these design steps, MARTE-based tools and methodologies are required. This paper presents a methodology to automatically generate SystemC heterogeneous executable specifications from generic MARTE models. To generate these specifications, the information included in the MARTE models is extracted to discover the system structure and hierarchy. A subset of the concurrency and communication features of the MARTE profile is used for this purpose. Then, automatic generation of the executable specification is possible. The code implementing the corresponding behavior can be easily integrated into the executable model. This design methodology proposes a refinement flow in order to perform the design steps before deciding the final system implementation.

A MDD methodology for specification of embedded systems and automatic generation of fast configurable and executable performance models

This paper presents the COMPLEX UML/MARTE modeling methodology and its related framework for automatic generation of executable performance models. The modeling methodology supports Model-Driven Development (MDD), required by industrial flows, and a novel set of modeling features specifically suitable for Design Space Exploration (DSE), a crucial design activity. The COMPLEX framework has other advantages for DSE. The COMPLEX tooling enables the automatic generation of an executable and configurable model for fast performance analysis without requiring engineering effort. The COMPLEX tooling automates the production of an easily portable text-based representation of the UML/MARTE model. This representation is read by the underlying simulation infrastructure, which automatically builds a fast performance model supporting the evaluation of different configurations of the system. An important aspect of this performance analysis framework is that it supports a system-level text-based front-end, which is produced from the COMPLEX UML/MARTE model, and which avoids the development of SW implementations, HW refinements, or the implementation of HW/SW interfaces. Moreover, neither code regeneration, nor recompilation is required for any DSE iterations, and thus, the time taken in the exploration is mostly due to model simulation.

Automatic synthesis of embedded SW for evaluating physical implementation alternatives from UML/MARTE models supporting memory space separation

Abstract The proposed approach presents a method for automatically synthesizing the SW code of complex embedded systems from a model-driven system specification. The solution is oriented to enabling easy exploration and design of different allocations of SW components in heterogeneous platforms, minimizing designer effort. The system is initially described following the UML/MARTE standard. Applying this standard, the system is modeled, describing its components, interfaces and communication links, the system memory spaces, the resource allocations and the HW architecture. From that information, a SW infrastructure containing the communication infrastructure is generated ad-hoc for the system depending on the HW architecture and the resource allocations evaluated. The consequent communication overhead reduction can result in an important advantage for system performance optimization.

Automatic synthesis from UML/MARTE models using channel semantics

Model-driven design is very common nowadays. In this context, the UML/MARTE profile is a well-known solution for real-time, embedded system modeling. This profile enables the functional and non-functional details of the system to be modeled together. Regarding non-functional details, the profile allows certain real-time constraints to be imposed when describing the system concurrency, in order to ensure predictability. However, these constraints also limit the modeling flexibility required to evaluate different design alternatives when optimizing system performance. The paper proposes a solution for automatically synthesizing the resulting models, combining new communication semantics with standard UML/MARTE real-time management features. The UML/MARTE approach presented in this paper enables concurrency and synchronization effects to be modeled at communication points, making system exploration and implementation easier.

CONTREX: Design of Embedded Mixed-Criticality CONTRol Systems under Consideration of EXtra-Functional Properties

The increasing processing power of todays HW/SW platforms leads to the integration of more and more functions in a single device. Additional design challenges arise when these functions share computing resources and belong to different criticality levels. The paper presents the CONTREX European project and its preliminary results. CONTREX complements current activities in the area of predictable computing platforms and segregation mechanisms with techniques to consider the extra-functional properties, i.e., timing constraints, power, and temperature. CONTREX enables energy efficient and cost aware design through analysis and optimization of these properties with regard to application demands at different criticality levels.

A model-based, single-source approach to design-space exploration and synthesis of mixed-criticality systems

While the Moores Law is still in place, the complexity of embedded systems continues to growth exponentially. Embedded Systems are implemented on complex HW/SW platforms, requiring more powerful design methods and tools. Electronic System Level (ESL) design [1] proposes to raise the level of abstraction in which the system is modeled in order to allow the analysis and optimization of the system at earlier stages of the design process.

Automatic deployment of component-based embedded systems from UML/MARTE models using MCAPI

The increasing complexity in the development of embedded system is raising the need of system modularization, parallelization and component portability. High-level languages such as UML are clearly oriented to solve these needs, but implementation flows are usually highly dependent on platform details. Different platform-agnostic APIs such as MPI or MCAPI have appeared to increase the application independence from the executive HW. Nevertheless, the gap between the high-level models and the final system implementations is still too large. In this context, this paper presents a methodology for automating system deployment of component-based systems. The process starts from a high level description based on UML/MARTE, including complex channel semantics and provides automatic code generation for interconnection and deployment of system components based on MCAPI. This automatic process enables exploring different possibilities both in the component allocation and in the resulting concurrency, involving low designer effort.

Automatic synthesis of communication and concurrency for exploring component-based system implementations considering UML channel semantics

Nowadays, multi-processor systems play a critical role in embedded system engineering. As a result, the generation of optimal concurrent implementations is an unavoidable but difficult task. Correct concurrent codes achieving maximum performance on the target platform are hard to obtain. On the one hand, dependencies on concurrent computations, such as shared variables or synchronizations, are extremely difficult to analyze from source code. On the other hand, it is completely unfeasible for designers to manually generate multiple implementations in order to evaluate and compare all the possible design alternatives. To overcome these limitations, this paper presents an automatic code generation approach focusing on communication channel semantics. The approach proposes the use of UML/MARTE models to enable designers to graphically handle dependencies and concurrency of the models. As a result, the automatic generation process enables multiple design alternatives to be easily obtained and evaluated without adding manual effort to the design process. To demonstrate these capabilities, the methodology is tested with two large examples.